公开(公告)号：US10109747B2

公开(公告)日：2018-10-23

申请号：US14831449

申请日：2015-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byong-Hyun Jang ,  Juhyung Kim ,  Woonkyung Lee ,  Jaegoo Lee ,  Chaeho Kim ,  Junkyu Yang ,  Phil Ouk Nam ,  Jaeyoung Ahn ,  Kihyun Hwang

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L29/04 ,  H01L29/10 ,  H01L23/528 ,  H01L29/51 ,  H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

公开(公告)号：US20240023340A1

公开(公告)日：2024-01-18

申请号：US18222278

申请日：2023-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhwan LIM ,  Yongseok Kim ,  Juhyung Kim ,  Minjun Lee

IPC: H10B51/30 ,  H10B51/10 ,  H10B51/40 ,  H10B80/00 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

CPC classification number: H10B51/30 ,  H10B51/10 ,  H10B51/40 ,  H10B80/00 ,  H01L25/0652 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H01L2225/06506

Abstract: The present disclosure provides methods, apparatuses, and systems for operating and manufacturing a semiconductor device. In some embodiments, a semiconductor device includes a stack structure including interlayer insulating layers and gate electrodes, a channel layer disposed inside a hole penetrating through the stack structure, a data storage layer disposed between the stack structure and the channel layer, data storage patterns disposed between the data storage layer and the gate electrodes, and dielectric layers disposed between the data storage patterns and the gate electrodes. The interlayer insulating layers and the gate electrodes are alternately and repeatedly stacked in a first direction. A first material of the data storage layer is different from a second material of the data storage patterns.

公开(公告)号：US09130054B2

公开(公告)日：2015-09-08

申请号：US13800872

申请日：2013-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byong-hyun Jang ,  Juhyung Kim ,  Woonkyung Lee ,  Jaegoo Lee ,  Chaeho Kim ,  Junkyu Yang ,  Phil Ouk Nam ,  Jaeyoung Ahn ,  Kihyun Hwang

IPC: H01L21/20 ,  H01L29/792 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/792 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

Abstract translation: 一种半导体存储器件及其制造方法。 该器件包括垂直堆叠在衬底的顶表面上的多个栅极，该衬底的顶表面上形成有在该衬底中形成的外延层，垂直穿过该栅极的垂直沟道以与该外延层电连接;以及存储层，设置在该垂直沟道 和大门。 外延层具有位于最下面一个栅极的底表面和基板的顶表面之间的高度的顶表面。