公开(公告)号：US20130059432A1

公开(公告)日：2013-03-07

申请号：US13667618

申请日：2012-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNWOO LEE ,  Sangwoo Lee ,  Changwon Lee ,  Jeonggil Lee

IPC: H01L21/28 ,  H01L21/20

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1159 ,  H01L29/4958 ,  H01L29/4966

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

公开(公告)号：US11244900B2

公开(公告)日：2022-02-08

申请号：US17029183

申请日：2020-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggil Lee ,  Sukhoon Kim ,  Sungmyong Park ,  Chanyang Lee ,  Honyun Park

IPC: H01L23/528 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11573

Abstract: A wiring structure includes first to third metal patterns on a substrate. The first metal pattern extends in a second direction and has a first width in a third direction. The second metal pattern extends in the third direction to cross the first metal pattern and have a second width in the second direction. The third metal pattern is connected to the first and second metal patterns at an area where the first and second metal patterns cross each other, and has a substantially rectangular shape with concave portions in each quadrant. The third metal pattern has a third width defined as a minimum distance between opposite ones of the concave portions in a fourth direction having an acute angle to the second and third directions, which is less or equal to than a smaller of the first and second widths.

公开(公告)号：US10199390B2

公开(公告)日：2019-02-05

申请号：US15644290

申请日：2017-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunwoo Lee ,  Sangwoo Lee ,  Changwon Lee ,  Jeonggil Lee

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/11578 ,  H01L29/49 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/1159

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

公开(公告)号：US09997400B2

公开(公告)日：2018-06-12

申请号：US15332297

申请日：2016-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangho Rha ,  Kyoung Hee Nam ,  Jeonggil Lee ,  Hyunseok Lim ,  Seungjong Park ,  Seulgi Bae ,  Jaejin Lee ,  Kwangtae Hwang

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76882 ,  H01L23/53238

Abstract: A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection provided on a second region of the substrate. A width of the second metal interconnection is greater than a width of the first metal interconnection. The first metal interconnection includes a metal pattern. The second metal interconnection includes a lower metal pattern having a concave surface at its top, an upper metal pattern disposed on the concave surface at the top of the lower metal pattern, and a first barrier pattern interposed between the lower metal pattern and the upper metal pattern. The metal interconnections are formed by a damascene process including deposition, reflow, metal implantation, and planarization processes.

公开(公告)号：US09082653B2

公开(公告)日：2015-07-14

申请号：US14561788

申请日：2014-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hauk Han ,  Yong-IL Kwon ,  JungSuk Oh ,  Tae sun Ryu ,  Jeonggil Lee

IPC: H01L27/115 ,  H01L29/788 ,  H01L23/52 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L23/52 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/4238 ,  H01L29/4941 ,  H01L29/788 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.

公开(公告)号：US20150035042A1

公开(公告)日：2015-02-05

申请号：US14486547

申请日：2014-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SunWoo Lee ,  Sangwoo Lee ,  Changwon Lee ,  Jeonggil Lee

IPC: H01L27/115 ,  H01L29/49

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1159 ,  H01L29/4958 ,  H01L29/4966

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

Abstract translation: 非易失性存储器件包括三维地布置在半导体衬底上的栅电极，从半导体衬底延伸并与栅电极的侧壁交叉的半导体图案，形成在半导体图案之间并形成在顶表面和底表面上的金属衬垫图案 以及形成在半导体图案和金属衬垫图案之间的电荷存储层。

公开(公告)号：US20250081462A1

公开(公告)日：2025-03-06

申请号：US18952236

申请日：2024-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk Han ,  Taeyong Kim ,  Keun Lee ,  Jeonggil Lee ,  Taisoo Lim ,  Hanmei Choi

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A semiconductor device includes gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of a substrate; interlayer insulating layers alternately stacked with the gate electrodes on the substrate; channel structures extending through the gate electrodes; and a separation region extending through the gate electrodes in the first direction and extending in a second direction perpendicular to the first direction, wherein each of the gate electrodes comprises a first conductive layer and a second conductive layer sequentially stacked, the second conductive layer including a metal nitride, and wherein the first conductive layer and the second conductive layer are each in physical contact with the separation region.

公开(公告)号：US12009300B2

公开(公告)日：2024-06-11

申请号：US17569774

申请日：2022-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggil Lee ,  Sukhoon Kim ,  Sungmyong Park ,  Chanyang Lee ,  Honyun Park

IPC: H01L23/528 ,  H01L21/768 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

Abstract: A wiring structure includes first to third metal patterns on a substrate. The first metal pattern extends in a second direction and has a first width in a third direction. The second metal pattern extends in the third direction to cross the first metal pattern and have a second width in the second direction. The third metal pattern is connected to the first and second metal patterns at an area where the first and second metal patterns cross each other, and has a substantially rectangular shape with concave portions in each quadrant. The third metal pattern has a third width defined as a minimum distance between opposite ones of the concave portions in a fourth direction having an acute angle to the second and third directions, which is less or equal to than a smaller of the first and second widths.

公开(公告)号：US09711523B2

公开(公告)日：2017-07-18

申请号：US14574456

申请日：2014-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggil Lee ,  Yeon-Sil Sohn ,  Woonghee Sohn ,  Kihyun Yoon ,  Myoungbum Lee ,  Tai-Soo Lim ,  Yong Chae Jung

IPC: H01L27/11582

CPC classification number: H01L27/11582

Abstract: Provided is a semiconductor device, including gate structures on a substrate, the gate structures extending parallel to a first direction and being spaced apart from each other by a separation trench interposed therebetween, each of the gate structures including insulating patterns stacked on the substrate and a gate electrode interposed therebetween; vertical pillars connected to the substrate through the gate structures; an insulating spacer in the separation trench covering a sidewall of each of the gate structures; and a diffusion barrier structure between the gate electrode and the insulating spacer.

公开(公告)号：US09245899B2

公开(公告)日：2016-01-26

申请号：US14740476

申请日：2015-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hauk Han ,  Yong-IL Kwon ,  JungSuk Oh ,  Tae sun Ryu ,  Jeonggil Lee

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L23/52 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/4238 ,  H01L29/4941 ,  H01L29/788 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.