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公开(公告)号:US12068369B2
公开(公告)日:2024-08-20
申请号:US18348904
申请日:2023-07-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jongsoon Park , Jongchul Park , Bokyoung Lee , Jeongyun Lee , Hyunggoo Lee , Yeondo Jung , Haegeon Jung
IPC: H01L29/06 , H01L27/088 , H01L29/423 , H01L29/786
CPC classification number: H01L29/0657 , H01L27/088 , H01L29/42392 , H01L29/78696
Abstract: A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch. The first distance may be about 0.8 times to about 1.2 times the first pitch.
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公开(公告)号:US20230352527A1
公开(公告)日:2023-11-02
申请号:US18348904
申请日:2023-07-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jongsoon PARK , Jongchul Park , Bokyoung Lee , Jeongyun Lee , Hyunggoo Lee , Yeondo Jung , Haegeon Jung
IPC: H01L29/06 , H01L27/088 , H01L29/786 , H01L29/423
CPC classification number: H01L29/0657 , H01L27/088 , H01L29/78696 , H01L29/42392
Abstract: A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch. The first distance may be about 0.8 times to about 1.2 times the first pitch.
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公开(公告)号:US11552176B2
公开(公告)日:2023-01-10
申请号:US17329361
申请日:2021-05-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sanghyun Lee , Sungwoo Kang , Jongchul Park , Youngmook Oh , Jeongyun Lee
IPC: H01L29/41 , H01L29/417 , H01L29/78 , H01L29/08 , H01L29/66 , H01L21/285 , H01L29/45
Abstract: An integrated circuit device includes a fin-type active area that extends on a substrate in a first direction, a gate structure that extends on the substrate in a second direction and crosses the fin-type active area, source/drain areas arranged on first and second sides of the gate structure, and a contact structure electrically connected to the source/drain areas. The source/drain areas comprise a plurality of merged source/drain structures. Each source/drain area comprises a plurality of first points respectively located on an upper surface of the source/drain area at a center of each source/drain structure, and each source/drain area comprises at least one second point respectively located on the upper surface of the source/drain area where side surfaces of adjacent source/drain structures merge with one another. A bottom surface of the contact structure is non-uniform and corresponds to the first and second points.
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公开(公告)号:US10205020B2
公开(公告)日:2019-02-12
申请号:US15348586
申请日:2016-11-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yongseok Lee , Jeongyun Lee , Gigwan Park , Keo Myoung Shin , Hyunji Kim , Sangduk Park
IPC: H01L29/78 , H01L29/66 , H01L27/092 , H01L29/06 , H01L29/423 , H01L21/8238 , H01L49/02 , H01L29/165
Abstract: A semiconductor device includes an active pattern having sidewalls defined by a device isolation pattern disposed on a substrate and an upper portion protruding from a top surface of the device isolation pattern, a liner insulating layer on the sidewalls of the active pattern, a gate structure on the active pattern, and source/drain regions at both sides of the gate structure. The liner insulating layer includes a first liner insulating layer and a second liner insulating layer having a top surface higher than a top surface of the first liner insulating layer. Each of the source/drain regions includes a first portion defined by the second liner insulating layer, and a second portion protruding upward from the second liner insulating layer and covering the top surface of the first liner insulating layer.
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公开(公告)号:US09954061B2
公开(公告)日:2018-04-24
申请号:US15605698
申请日:2017-05-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jeongyun Lee , Kwang-Yong Yang , Keomyoung Shin , Jinwook Lee , Yongseok Lee
IPC: H01L27/088 , H01L29/10 , H01L29/06 , H01L29/423 , H01L29/40 , H01L29/66 , H01L21/8234 , H01L29/49 , H01L29/51
CPC classification number: H01L29/1033 , H01L21/823412 , H01L29/0649 , H01L29/0673 , H01L29/401 , H01L29/42364 , H01L29/4966 , H01L29/513 , H01L29/66439 , H01L29/6653 , H01L29/6656
Abstract: A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern.
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