公开(公告)号：US11715684B2

公开(公告)日：2023-08-01

申请号：US17376240

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin Hwang ,  Jiwon Kim ,  Jaeho Ahn ,  Joonsung Lim ,  Sukkang Sung

IPC: H01L27/115 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B43/27

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L24/20 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/2105 ,  H01L2224/24146 ,  H01L2924/1431 ,  H01L2924/14511 ,  H10B43/27

Abstract: A semiconductor device includes lower circuit patterns on a lower substrate; lower bonding patterns on the lower circuit patterns, the lower bonding patterns including a conductive material and being electrically connected to the lower circuit patterns; upper bonding patterns on and contacting the lower bonding patterns, and including a conductive material; a passive device on the upper bonding patterns, and including a conductive material and contacting one of the upper bonding patterns; a gate electrode structure on the passive device, and including gate electrodes spaced apart from each other in a first direction, each of which extends in a second direction, and extension lengths in the second direction of the gate electrodes increasing from a lowermost level toward an uppermost level in a stepwise manner; a channel extending through at least a portion of the gate electrode structure; and an upper substrate on the channel.

公开(公告)号：US20230052161A1

公开(公告)日：2023-02-16

申请号：US17873739

申请日：2022-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyeong Seok ,  Younggul Song ,  Eunchu Oh ,  Byungchul Jang ,  Joonsung Lim

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/16 ,  G11C16/08

Abstract: In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.

公开(公告)号：US11581333B2

公开(公告)日：2023-02-14

申请号：US17573015

申请日：2022-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Ahn ,  Woosung Yang ,  Joonsung Lim ,  Sungmin Hwang

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11526 ,  H01L23/522 ,  H01L25/065 ,  H01L23/00 ,  H01L27/11573

Abstract: An integrated circuit device includes: a lower memory stack including a plurality of lower word lines located on a substrate, an upper memory stack located on the lower memory stack and including a plurality of upper word lines, at least one first lower interconnection layer extending in a horizontal direction at a first vertical level between the lower memory stack and the upper memory stack, and configured to be electrically connected to at least one lower word line selected from the plurality of lower word lines, a separate insulating film covering at least one first lower interconnection layer, and at least one first upper interconnection layer extending in the horizontal direction at a second vertical level higher than the upper memory stack, and configured to be electrically connected to at least one upper word line selected from the upper word lines.

公开(公告)号：US11450684B2

公开(公告)日：2022-09-20

申请号：US17007141

申请日：2020-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woosung Yang ,  Byungjin Lee ,  Bumkyu Kang ,  Joonsung Lim

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11519 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11526 ,  G11C7/18 ,  H01L23/522 ,  H01L27/11524

Abstract: A memory device includes a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes a peripheral circuit, and an upper bonding pad disposed on a top surface of the lower structure. Each of the plurality of upper structures includes a bit line, a through via, and a lower bonding pad disposed on a bottom surface of the upper structures and connected to the through via. Each of upper structures, other than an uppermost upper structure, further includes an upper bonding pad disposed on a top surface thereof and connected to the through via. The bit line includes a gap separating a first portion of the bit line from a second portion thereof in the horizontal direction, and the through via overlaps the gap of the bit line in a plan view.

公开(公告)号：US20220173060A1

公开(公告)日：2022-06-02

申请号：US17470644

申请日：2021-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Ahn ,  Jiwon Kim ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A nonvolatile memory device and a data storage system including the same are provided. The nonvolatile memory device includes: a first structure including at least one first memory plane; and a second structure bonded to the first structure and including at least one second memory plane, wherein the number of the at least one first memory plane included in the first structure is different from the number of the at least one second memory plane included in the second structure.

公开(公告)号：US20220157838A1

公开(公告)日：2022-05-19

申请号：US17467568

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Ahn ,  Jiwon Kim ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: H01L27/11524 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device and a data storage system including the same, the semiconductor device including: a first structure including a peripheral circuit; and a second structure, including: a pattern structure; an upper insulating layer; a stack structure between the first structure and the pattern structure and including first and second stack portions spaced apart from each other, the first and second stack portions respectively including horizontal conductive layers and interlayer insulating layers alternately stacked; separation structures penetrating through the stack structure; memory vertical structures penetrating through the first stack portion; and a contact structure penetrating through the second stack portion, the pattern structure, and the upper insulating layer, wherein the contact structure includes a lower contact plug penetrating through at least the second stack portion and an upper contact plug contacting the lower contact plug and extending upwardly to penetrate through the pattern structure and the upper insulating layer.

公开(公告)号：US20250124984A1

公开(公告)日：2025-04-17

申请号：US19002360

申请日：2024-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Ahn ,  Jiwon Kim ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: G11C16/10 ,  G11C16/26 ,  H01L23/48 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes: a semiconductor substrate having a first surface and a second surface opposing each other; a back-side insulating layer below the second surface of the semiconductor substrate; an external input/output conductive pattern below the back-side insulating layer; a circuit device including a gate electrode and a source/drain region, on the first surface of the semiconductor substrate; an internal input/output conductive pattern on the first surface of the semiconductor substrate, the internal input/output conductive pattern having at least a portion disposed on the same level as at least a portion of the gate electrode; a through-electrode structure penetrating through the semiconductor substrate and the back-side insulating layer and electrically connected to the internal input/output conductive pattern and the external input/output conductive pattern; and a memory cell array region disposed on a level higher than the circuit device, on the first surface of the semiconductor substrate.

公开(公告)号：US12057421B2

公开(公告)日：2024-08-06

申请号：US17470644

申请日：2021-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Ahn ,  Jiwon Kim ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A nonvolatile memory device and a data storage system including the same are provided. The nonvolatile memory device includes: a first structure including at least one first memory plane; and a second structure bonded to the first structure and including at least one second memory plane, wherein the number of the at least one first memory plane included in the first structure is different from the number of the at least one second memory plane included in the second structure.

公开(公告)号：US11967574B2

公开(公告)日：2024-04-23

申请号：US17460873

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin Hwang ,  Jiwon Kim ,  Jaeho Ahn ,  Joonsung Lim ,  Sukkang Sung

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device including a first structure; and a second structure on the first structure, wherein the first structure includes a first substrate; a peripheral circuit on the first substrate; a first insulating layer covering the first substrate and the peripheral circuit; and a first bonding pad on the first insulating layer, the second structure includes a second substrate; a memory cell array on a first surface of the second substrate; a second insulating layer covering the first surface of the second substrate and the memory cell array; a conductive pattern at least partially recessed from a second surface of the second substrate; and a second bonding pad on the second insulating layer, the first bonding pad is in contact with the second bonding pad, and the conductive pattern is spaced apart from the second insulating layer.

公开(公告)号：US11955470B2

公开(公告)日：2024-04-09

申请号：US17229062

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Jaeho Ahn ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: H01L23/00 ,  H01L25/18 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L25/18 ,  H01L24/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H01L2224/08147 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: A semiconductor device includes a first peripheral circuit region comprising a plurality of lower circuitries, a second peripheral circuit region apart from the first peripheral circuit region in a vertical direction, the second peripheral circuit region comprising a plurality of upper circuitries, and a cell region comprising a plurality of word lines, the cell region between the first peripheral circuit region and the second peripheral circuit region in the vertical direction. The plurality of word lines comprise a first word line connected to a first lower circuitry selected from the plurality of lower circuitries and a second word line connected to a first upper circuitry selected from the plurality of upper circuitries.