公开(公告)号：US20160358920A1

公开(公告)日：2016-12-08

申请号：US14990992

申请日：2016-01-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn KIM

IPC: H01L27/092 ,  H01L29/423 ,  H01L27/11 ,  H01L29/49 ,  H01L27/108

CPC classification number: H01L27/1104 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/108 ,  H01L27/1116 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor device includes first through fourth areas, first through fourth gate stacks, the first gate stack includes a first high-dielectric layer, a first TiN layer to contact the first high-dielectric layer, and a first gate metal on the first TiN layer, the second gate stack includes a second high-dielectric layer, a second TiN layer to contact the second high-dielectric layer, and a second gate metal on the second TiN layer, the third gate stack includes a third high-dielectric layer, a third TiN layer to contact the third high-dielectric layer, and a third gate metal on the third TiN layer, and the fourth gate stack includes a fourth high-dielectric layer, a fourth TiN layer to contact the fourth high-dielectric layer, and a fourth gate metal on the fourth TiN layer, the first through fourth thicknesses of the TiN layers being different.

Abstract translation: 半导体器件包括第一至第四区域，第一至第四栅极堆叠，第一栅极堆叠包括第一高电介质层，与第一高电介质层接触的第一TiN层和第一TiN层上的第一栅极金属 所述第二栅叠层包括第二高电介质层，与所述第二高电介质层接触的第二TiN层和所述第二TiN层上的第二栅极金属，所述第三栅叠层包括第三高电介质层， 第三TiN层与第三高电介质层接触，第三栅极金属在第三TiN层上，第四栅叠层包括第四高电介质层，与第四高电介质层接触的第四TiN层，以及 在第四TiN层上的第四栅极金属，TiN层的第一至第四厚度不同。

公开(公告)号：US20160358913A1

公开(公告)日：2016-12-08

申请号：US14990951

申请日：2016-01-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn KIM

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966

Abstract: Semiconductor devices are provided. The semiconductor device includes a first fin portion and a second fin portion arranged on a substrate and extended in a first direction, the first fin portion and the second fin portion being spaced apart from each other in the first direction, a field insulating layer between the first fin portion and the second fin portion and having an upper surface thereof lower than an upper surface of the first fin portion, a first metal gate extended in a second direction on the first fin portion and a silicon gate extended in the second direction on the field insulating layer and contacting the field insulating layer.

Abstract translation: 提供半导体器件。 所述半导体器件包括：第一鳍部和布置在基板上并沿第一方向延伸的第二鳍部，所述第一鳍部和所述第二鳍部在所述第一方向上彼此间隔开， 第一鳍片部分和第二鳍片部分，并且其上表面低于第一鳍片部分的上表面;第一金属栅极，其在第一鳍片部分上沿第二方向延伸;以及硅栅极，沿着第二方向延伸， 并且与场绝缘层接触。

公开(公告)号：US20190221564A1

公开(公告)日：2019-07-18

申请号：US16366140

申请日：2019-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn KIM ,  Hyun-Jo KIM ,  Hwa-Sung RHEE

IPC: H01L27/088 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.

公开(公告)号：US20150364574A1

公开(公告)日：2015-12-17

申请号：US14579627

申请日：2014-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Youn KIM ,  Dong-Hyun ROH ,  Sang-Duk PARK ,  Il-Young YOON ,  Jeong-Nam HAN ,  Jong-Mil YOUN

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/3213 ,  H01L27/088 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/66636

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure including a dummy gate insulation layer pattern, a dummy gate electrode and a gate mask sequentially stacked are formed on a substrate. An interlayer insulating layer including tonen silazane (TOSZ) is formed on the substrate to cover the dummy gate structure. An upper portion of the interlayer insulating layer is planarized until a top surface of the gate mask is exposed to form an interlayer insulating layer pattern. The exposed gate mask, and the dummy gate electrode and the dummy gate insulation layer pattern under the gate mask are removed to form an opening exposing a top surface of the substrate. The dummy gate insulation layer pattern is removed using an etchant including hydrogen fluoride (HF), but the interlayer insulating layer pattern remains. A gate structure is formed to fill the opening.

Abstract translation: 在制造半导体器件的方法中，在衬底上形成包括虚拟栅极绝缘层图案，虚拟栅极电极和栅极掩模的虚拟栅极结构。 在基板上形成包含蒙片硅氮烷（TOSZ）的层间绝缘层，以覆盖虚拟栅极结构。 层间绝缘层的上部被平坦化，直到露出栅极掩模的顶表面以形成层间绝缘层图案。 除去栅极掩模下的露出的栅极掩模，伪栅极电极和伪栅极绝缘层图案，以形成露出衬底顶表面的开口。 使用包括氟化氢（HF）的蚀刻剂去除伪栅极绝缘层图案，但是残留层间绝缘层图案。 形成浇口结构以填充开口。

公开(公告)号：US20150102418A1

公开(公告)日：2015-04-16

申请号：US14576268

申请日：2014-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn KIM

IPC: H01L27/11 ,  H01L29/51 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device includes a N-type field effect transistor comprising a N-channel region in a substrate. A high dielectric constant (high-k) layer is disposed on the N-channel region. A diffusion layer including a metal oxide is disposed on the high-k layer. A passivation layer is disposed on the diffusion layer, and a first metal gate is disposed on the passivation layer. The first high-k layer and the N-channel region include metal atoms of a metal element of the metal oxide.

Abstract translation: 半导体器件包括在衬底中包括N沟道区的N型场效应晶体管。 高介电常数（高k）层设置在N沟道区上。 包含金属氧化物的扩散层设置在高k层上。 钝化层设置在扩散层上，第一金属栅极设置在钝化层上。 第一高k层和N沟道区包括金属氧化物的金属元素的金属原子。

公开(公告)号：US20140167177A1

公开(公告)日：2014-06-19

申请号：US14081543

申请日：2013-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hun KIM ,  Ju-Youn KIM ,  Koung-Min RYU ,  Jong-Mil YOUN ,  Jong-Ho LEE

IPC: H01L27/11 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1029

Abstract: A semiconductor device includes a channel layer over an active region, first and second field regions adjacent the active region, and a gate structure over the channel layer and portions of the first and second field regions. The first and second field regions include grooves adjacent respective sidewalls of the channel layer, and bottom surfaces of the grooves are below a bottom surface of the channel layer.

Abstract translation: 半导体器件包括在有源区上的沟道层，与有源区相邻的第一和第二场区以及沟道层上的栅极结构以及第一和第二场区的部分。 第一和第二场区域包括与沟道层的相应侧壁相邻的沟槽，并且沟槽的底表面在沟道层的底表面下方。

公开(公告)号：US20140099784A1

公开(公告)日：2014-04-10

申请号：US13647577

申请日：2012-10-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn KIM ,  JE-DON KIM

IPC: H01L21/3205

CPC classification number: H01L27/092 ,  H01L21/02068 ,  H01L21/28088 ,  H01L21/28247 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/0642 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for manufacturing a semiconductor device includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern and a second metal gate film pattern in the trench, redepositing a second metal gate film on the first and second metal gate film patterns and the insulation film, and forming a redeposited second metal gate film pattern on the first and second metal gate film patterns by performing a planarization process for removing a portion of the redeposited second metal gate film so as to expose a top surface of the insulation film, and forming a blocking layer pattern on the redeposited second metal gate film pattern by oxidizing an exposed surface of the redeposited second metal gate film pattern.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成包括沟槽的绝缘膜，在沟槽中形成第一金属栅极膜图案和第二金属栅极膜图案，在第一和第二金属栅极上再沉积第二金属栅极膜 膜图案和绝缘膜，并且通过执行用于去除一部分再沉积的第二金属栅极膜的平坦化工艺在第一和第二金属栅极膜图案上形成再沉积的第二金属栅极膜图案，以暴露出第二金属栅极膜的顶表面 并且通过氧化再沉积的第二金属栅极膜图案的暴露表面，在再沉积的第二金属栅极膜图案上形成阻挡层图案。