-
公开(公告)号:US10685695B2
公开(公告)日:2020-06-16
申请号:US16405219
申请日:2019-05-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Chang Hoon Jeon , Yong Seok Kim , Jun Hee Lim
IPC: G11C5/02 , G11C11/40 , G11C16/04 , H01L21/8234 , H01L21/8238 , H01L27/092 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L29/49 , H01L29/51
Abstract: A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.
-
公开(公告)号:US20240164106A1
公开(公告)日:2024-05-16
申请号:US18465405
申请日:2023-09-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dong Jin Lee , Jun Hee Lim , Kang-Oh Yun
Abstract: A semiconductor device is provided. The semiconductor device includes an active region, a first source/drain region disposed on the active region, a first contact on the first source/drain region, a second source/drain region spaced apart from the first source/drain region and disposed on the active region, a second contact on the second source/drain region and a first gate electrode disposed on the active region. The first gate electrode includes a first ring portion, which surrounds the first contact, but the second contact extends outside the first ring portion.
-
公开(公告)号:US20240121963A1
公开(公告)日:2024-04-11
申请号:US18474307
申请日:2023-09-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: So Hyun Lee , Kang-Oh Yun , Dong Jin Lee , Jun Hee Lim
Abstract: A semiconductor memory device includes: a substrate including a first region and a second region, the first region includes a peripheral circuit and a first active region (FAR), and the second region includes memory cell blocks. The FAR includes a FAR first extension extending in a first direction, a FAR second extension extending in a second direction, and a FAR third extension extending in a third direction. The FAR first extension, the FAR second extension, and the FAR third extension form an angle greater than 90 degrees relative to one another. The device includes a first pass transistor circuit configured to transmit driving signals, and the first pass transistor circuit includes a FAR first gate structure on the FAR first extension, a FAR second gate structure on the FAR second extension, a FAR third gate structure on the FAR third extension, and a first shared source/drain.
-
公开(公告)号:US10998301B2
公开(公告)日:2021-05-04
申请号:US16531778
申请日:2019-08-05
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kohji Kanamori , Hyun Mog Park , Yong Seok Kim , Kyung Hwan Lee , Jun Hee Lim , Jee Hoon Han
IPC: H01L25/18 , H01L23/00 , H01L27/11556 , H01L27/11582
Abstract: A semiconductor device includes a first semiconductor structure including circuit devices and first bonding pads; and a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure including a base layer; a first memory cell structure including first gate electrodes and first channels penetrating through the first gate electrodes; a second memory cell structure including second gate electrodes and second channels penetrating through the second gate electrodes; bit lines between the first and the second memory cell structures, and electrically connected to the first and second channels in common; first and second conductive layers on the second surface of the base layer; a pad insulating layer having an opening exposing a portion of the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in a lower portion of the second memory cell structure.
-
公开(公告)号:US10916543B2
公开(公告)日:2021-02-09
申请号:US16726322
申请日:2019-12-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seung Uk Han , Taek Yong Kim , Satoru Yamada , Jun Hee Lim , Ki Jae Hur
IPC: H01L27/088 , H01L27/092 , H01L21/8238 , H01L21/762 , G11C11/408 , H01L29/423 , H01L23/522 , H01L23/528 , G11C11/4097 , H01L27/02
Abstract: A semiconductor device includes first and second active regions extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction, wherein the first and second active regions overlaps with each other in the second direction, a third active region extending in the first direction on the substrate and spaced apart from the first active region in the second direction. The first active region is positioned between the second and third active regions in the second direction. The first and third active regions partially overlap in the second direction, and a device isolation film is configured to define the first to third active regions.
-
公开(公告)号:US20190267088A1
公开(公告)日:2019-08-29
申请号:US16059317
申请日:2018-08-09
Applicant: Samsung Electronics Co., Ltd.
Inventor: Chang Hoon JEON , Yoo Cheol Shin , Jun Hee Lim , Sung Kweon Baek , Chan Ho Lee , Won Chul Jang , Sun Gyung Hwang
IPC: G11C14/00 , G11C11/401 , H01L27/108 , H01L23/532
Abstract: A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.
-
公开(公告)号:US12178046B2
公开(公告)日:2024-12-24
申请号:US18347973
申请日:2023-07-06
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kohji Kanamori , Yong Seok Kim , Kyung Hwan Lee , Jun Hee Lim , Jee Hoon Han
IPC: H10B43/27 , G11C16/04 , G11C16/08 , H01L23/528 , H01L25/00 , H01L25/18 , H01L29/10 , H01L29/78 , H10B43/40
Abstract: A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line.
-
公开(公告)号:US11088163B2
公开(公告)日:2021-08-10
申请号:US16527506
申请日:2019-07-31
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kohji Kanamori , Yong Seok Kim , Kyung Hwan Lee , Jun Hee Lim , Jee Hoon Han
IPC: H01L27/11582 , H01L23/528 , H01L25/18 , H01L27/11573 , H01L25/00 , G11C16/08 , H01L29/78 , H01L29/10 , G11C16/04
Abstract: A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line.
-
公开(公告)号:US10685708B2
公开(公告)日:2020-06-16
申请号:US16059317
申请日:2018-08-09
Applicant: Samsung Electronics Co., Ltd.
Inventor: Chang Hoon Jeon , Yoo Cheol Shin , Jun Hee Lim , Sung Kweon Baek , Chan Ho Lee , Won Chul Jang , Sun Gyung Hwang
IPC: G11C14/00 , G11C11/401 , H01L27/108 , H01L23/532 , H01L27/11582 , H01L27/105 , H01L27/11573
Abstract: A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.
-
公开(公告)号:US20200161301A1
公开(公告)日:2020-05-21
申请号:US16726322
申请日:2019-12-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seung Uk Han , Taek Yong Kim , Satoru Yamada , Jun Hee Lim , Ki Jae Hur
IPC: H01L27/092 , H01L21/762 , H01L21/8238 , G11C11/408
Abstract: A semiconductor device includes first and second active regions extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction, wherein the first and second active regions overlaps with each other in the second direction, a third active region extending in the first direction on the substrate and spaced apart from the first active region in the second direction. The first active region is positioned between the second and third active regions in the second direction. The first and third active regions partially overlap in the second direction, and a device isolation film is configured to define the first to third active regions.
-
-
-
-
-
-
-
-
-