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公开(公告)号：US09935111B2
公开(公告)日：2018-04-03
申请号：US15631105
申请日：2017-06-23
发明人： Eunjung Kim , Sohyun Park , Bong-Soo Kim , Yoosang Hwang , Dong-Wan Kim , Junghoon Han
IPC分类号： H01L21/20 , H01L27/108
CPC分类号： H01L27/10894 , H01L21/0274 , H01L21/31051 , H01L21/31144 , H01L21/565 , H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10897 , H01L27/11582 , H01L28/00 , H01L28/60
摘要： A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer.
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公开(公告)号：US11817408B2
公开(公告)日：2023-11-14
申请号：US18093880
申请日：2023-01-06
发明人： Minjung Choi , Sooho Shin , Yeonjin Lee , Junghoon Han
CPC分类号： H01L24/05 , H01L21/561 , H01L24/13 , H01L24/73 , H01L24/96 , H01L2224/0401 , H01L2224/12105 , H01L2224/13099 , H01L2224/81801 , H01L2924/1304 , H01L2924/18162
摘要： A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.
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公开(公告)号：US11769742B2
公开(公告)日：2023-09-26
申请号：US17747190
申请日：2022-05-18
发明人： Eunyoung Jeong , Juik Lee , Junghoon Han
IPC分类号： H01L23/00
CPC分类号： H01L24/05 , H01L2224/05583
摘要： Disclosed embodiments include a semiconductor chip including a semiconductor substrate having a top surface with a top connection pad disposed therein, and a protection insulation layer comprising an opening therein, the protection insulation layer not covering at least a portion of the top connection pad, on the semiconductor substrate. The protection insulation layer may include: a bottom protection insulation layer, a cover insulation layer comprising a side cover part that covers at least a portion of a side surface of the bottom protection insulation layer and a top cover part disposed apart from the side cover part to cover at least a portion of a top surface of the bottom protection insulation layer. The protection insulation layer may further include a top protection insulation layer on the top cover part.
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公开(公告)号：US11758713B2
公开(公告)日：2023-09-12
申请号：US17386008
申请日：2021-07-27
发明人： Dongoh Kim , Gyuhyun Kil , Junghoon Han , Doosan Back
IPC分类号： H10B12/00 , H01L27/092
CPC分类号： H10B12/50 , H01L27/092 , H10B12/315
摘要： A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.
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公开(公告)号：US20210134745A1
公开(公告)日：2021-05-06
申请号：US16922828
申请日：2020-07-07
发明人： Eunyoung Jeong , Juik Lee , Junghoon Han
IPC分类号： H01L23/00
摘要： Disclosed embodiments include a semiconductor chip including a semiconductor substrate having a top surface with a top connection pad disposed therein, and a protection insulation layer comprising an opening therein, the protection insulation layer not covering at least a portion of the top connection pad, on the semiconductor substrate. The protection insulation layer may include: a bottom protection insulation layer, a cover insulation layer comprising a side cover part that covers at least a portion of a side surface of the bottom protection insulation layer and a top cover part disposed apart from the side cover part to cover at least a portion of a top surface of the bottom protection insulation layer. The protection insulation layer may further include a top protection insulation layer on the top cover part.
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公开(公告)号：US20210057328A1
公开(公告)日：2021-02-25
申请号：US16848246
申请日：2020-04-14
发明人： Yeonjin Lee , Junyong Noh , Minjung Choi , Junghoon Han , Yunrae Cho
IPC分类号： H01L23/522 , H01L23/31 , H01L23/48 , H01L23/00 , H01L23/528
摘要： A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.
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公开(公告)号：US12062624B2
公开(公告)日：2024-08-13
申请号：US17391659
申请日：2021-08-02
发明人： Chulsoon Chang , Sangki Kim , Ilgeun Jung , Junghoon Han
IPC分类号： H01L21/768 , H01L23/00
CPC分类号： H01L23/562 , H01L21/76877
摘要： A semiconductor device may include a semiconductor substrate, a crack-blocking layer and a crack-blocking portion. The semiconductor substrate may include a plurality of chip regions and a scribe lane region configured to surround each of the plurality of the chip regions. A trench may be defined by one or more inner surfaces of the semiconductor device to be formed in the scribe lane region. The crack-blocking layer may be on an inner surface of the trench. The crack-blocking layer may be configured to block a spreading of a crack, which is generated in the scribe lane region during a cutting of the semiconductor substrate along the scribe lane region, from spreading into any of the chip regions. The crack-blocking portion may at least partially fill the trench and may be configured to block the spreading of the crack from the scribe lane region into any of the chip regions.
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公开(公告)号：US11792976B2
公开(公告)日：2023-10-17
申请号：US17371558
申请日：2021-07-09
发明人： Dongoh Kim , Gyuhyun Kil , Junghoon Han , Doosan Back
IPC分类号： H10B12/00
CPC分类号： H10B12/50 , H10B12/0335 , H10B12/053 , H10B12/09 , H10B12/315 , H10B12/34 , H10B12/482 , H10B12/485
摘要： A semiconductor memory device may have a substrate including an active region in a memory cell region and a logic active region in a peripheral region, an element isolation structure between the active region and the logic active region, an insulating layer pattern covering the active region, and a support insulating layer. The insulating layer pattern may include an extension portion that extends along the element isolation structure, may be spaced apart from the element isolation structure, and may overhang over the element isolation structure. The support insulating layer may fill a recess space defined between the extension portion and the element isolation structure.
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公开(公告)号：US11769737B2
公开(公告)日：2023-09-26
申请号：US17319232
申请日：2021-05-13
发明人： Junghoon Han , Jongmin Lee
CPC分类号： H01L23/562 , H01L21/4853 , H01L21/563 , H01L23/13 , H01L23/3157 , H01L23/49838 , H01L23/49894 , H01L24/16 , H01L2224/16227 , H01L2924/18161 , H01L2924/3512
摘要： A semiconductor package includes an upper conductive pattern and a redistribution layer on a first surface of a substrate, a semiconductor chip facing the first surface of the substrate, the semiconductor chip being spaced apart from the first surface of the substrate, a conductive bump bonding between the semiconductor chip and the upper conductive pattern, the conductive bump electrically connecting the semiconductor chip and the upper conductive pattern, and an upper passivation layer on the redistribution layer, a portion of the upper passivation layer facing an edge of a lower surface of the semiconductor chip.
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20.发明授权公开(公告)号：US11756843B2
公开(公告)日：2023-09-12
申请号：US17706401
申请日：2022-03-28
发明人： Minjung Choi , Junyong Noh , Yeonjin Lee , Junghoon Han
摘要： A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall.
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