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    Semiconductor devices
    11.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US12142690B2

    公开(公告)日：2024-11-12

    申请号：US18588163

    申请日：2024-02-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Taek Kim ,  Seok Hoon Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong ,  Min-Hee Choi ,  Ryong Ha

    IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

    Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.

    SEMICONDUCTOR DEVICES
    12.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240194789A1

    公开(公告)日：2024-06-13

    申请号：US18588163

    申请日：2024-02-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Taek Kim ,  Seok Hoon Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong ,  Min-Hee Choi ,  Ryong Ha

    IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

    CPC classification number: H01L29/78618 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

    Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.

    Semiconductor devices having variously-shaped source/drain patterns
    13.
    发明授权
    Semiconductor devices having variously-shaped source/drain patterns 有权

    公开(公告)号：US11942528B2

    公开(公告)日：2024-03-26

    申请号：US18196533

    申请日：2023-05-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Kwan Yu ,  Min-Hee Choi

    IPC: H01L29/417 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088

    CPC classification number: H01L29/41791 ,  H01L21/76224 ,  H01L21/823425 ,  H01L21/823431 ,  H01L27/0886

    Abstract: A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.

    SEMICONDUCTOR DEVICES
    15.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220190168A1

    公开(公告)日：2022-06-16

    申请号：US17519967

    申请日：2021-11-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Taek Kim ,  Seok Hoon Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong ,  Min-Hee Choi ,  Ryong Ha

    IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

    Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.

    Semiconductor devices having variously-shaped source/drain patterns
    16.
    发明授权
    Semiconductor devices having variously-shaped source/drain patterns 有权

    公开(公告)号：US11688781B2

    公开(公告)日：2023-06-27

    申请号：US17131977

    申请日：2020-12-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Kwan Yu ,  Min-Hee Choi

    IPC: H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762

    CPC classification number: H01L29/41791 ,  H01L21/76224 ,  H01L21/823425 ,  H01L21/823431 ,  H01L27/0886

    Abstract: A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.

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