公开(公告)号：US09275995B2

公开(公告)日：2016-03-01

申请号：US14543140

申请日：2014-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum Kim ,  Bon-Young Koo ,  Seok-Hoon Kim ,  Chul Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Su-Jin Jung

IPC: H01L27/088 ,  H01L29/161 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/785

Abstract: An integrated circuit device includes an electrically conductive pattern on a substrate. This electrically conductive pattern may be a gate pattern of a field effect transistor. A first electrically insulating spacer is provided on a sidewall of the electrically conductive pattern. The first electrically insulating spacer includes a first lower spacer and a first upper spacer, which extends on the first lower spacer and has a side surface vertically aligned with a corresponding side surface of the first lower spacer. The first upper spacer has a greater dielectric constant relative to a dielectric constant of the first lower spacer. A pair of parallel channel regions may also be provided, which protrude from a surface of the substrate. The electrically conductive pattern may surround top and side surfaces of the pair of parallel channel regions.

Abstract translation: 集成电路器件包括在衬底上的导电图案。 该导电图案可以是场效应晶体管的栅极图案。 第一电绝缘垫片设置在导电图案的侧壁上。 第一电绝缘间隔件包括第一下间隔件和第一上间隔件，其在第一下间隔件上延伸并且具有与第一下间隔件的对应侧表面垂直对准的侧表面。 第一上间隔物相对于第一下间隔物的介电常数具有更大的介电常数。 还可以设置一对平行的通道区域，其从衬底的表面突出。 导电图案可以围绕该对平行通道区域的顶表面和侧表面。

公开(公告)号：US10147723B2

公开(公告)日：2018-12-04

申请号：US15653733

申请日：2017-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Hoon Kim ,  Jin-Bum Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Jin-Hee Han ,  Bon-Young Koo

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/78 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417

Abstract: A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.

公开(公告)号：US20160284703A1

公开(公告)日：2016-09-29

申请号：US15177421

申请日：2016-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Hoon Kim ,  Jin-Bum Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Jin-Hee Han ,  Bon-Young Koo

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.

公开(公告)号：US11469237B2

公开(公告)日：2022-10-11

申请号：US16388347

申请日：2019-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum Kim ,  Myung-Gil Kang ,  Kang-Hun Moon ,  Cho-Eun Lee ,  Su-Jin Jung ,  Min-Hee Choi ,  Yang Xu ,  Dong-Suk Shin ,  Kwan-Heum Lee ,  Hoi-Sung Chung

IPC: H01L27/088 ,  H01L27/11 ,  H01L29/66 ,  H01L29/78 ,  H01L23/485 ,  H01L21/8234 ,  H01L29/417 ,  H01L23/528 ,  H01L29/08 ,  H01L29/161 ,  H01L29/45 ,  H01L27/092 ,  H01L29/165

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US20190244963A1

公开(公告)日：2019-08-08

申请号：US16388347

申请日：2019-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum Kim ,  Myung-Gil Kang ,  Kang-Hun Moon ,  Cho-Eun Lee ,  Su-Jin Jung ,  Min-Hee Choi ,  Yang Xu ,  Dong-Suk Shin ,  Kwan-Heum Lee ,  Hoi-Sung Chung

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/161 ,  H01L29/78 ,  H01L29/08 ,  H01L23/528 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/485 ,  H01L29/45

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/5283 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US10297601B2

公开(公告)日：2019-05-21

申请号：US15351739

申请日：2016-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum Kim ,  Myung-Gil Kang ,  Kang-Hun Moon ,  Cho-Eun Lee ,  Su-Jin Jung ,  Min-Hee Choi ,  Yang Xu ,  Dong-Suk Shin ,  Kwan-Heum Lee ,  Hoi-Sung Chung

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78 ,  H01L23/528 ,  H01L27/088 ,  H01L29/08 ,  H01L29/161 ,  H01L29/45 ,  H01L23/485 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/092 ,  H01L29/165

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US09735158B2

公开(公告)日：2017-08-15

申请号：US15177421

申请日：2016-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Hoon Kim ,  Jin-Bum Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Jin-Hee Han ,  Bon-Young Koo

IPC: H01L27/108 ,  H01L27/088 ,  H01L27/02 ,  H01L29/78 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.

公开(公告)号：US20130171818A1

公开(公告)日：2013-07-04

申请号：US13728622

申请日：2012-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum Kim ,  Young-Pil Kim ,  Kwan-Heum Lee ,  Sun-Ghil Lee

IPC: H01L21/285

CPC classification number: H01L21/285 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76889 ,  H01L27/10855 ,  H01L28/91

Abstract: In a method of forming an ohmic layer of a DRAM device, the metal silicide layer between the storage node contact plug and the lower electrode of a capacitor is formed as the ohmic layer by a first heat treatment under a first temperature and an instantaneous second heat treatment under a second temperature higher than the first temperature. Thus, the metal silicide layer has a thermo-stable crystal structure and little or no agglomeration occurs on the metal silicide layer in the high temperature process. Accordingly, the sheet resistance of the ohmic layer may not increase in spite of the subsequent high temperature process.

Abstract translation: 在形成DRAM器件的欧姆层的方法中，通过在第一温度和瞬时第二次加热下的第一次热处理将存储节点接触插塞和电容器的下部电极之间的金属硅化物层形成为欧姆层 在比第一温度高的第二温度下进行处理。 因此，金属硅化物层具有热稳定的晶体结构，并且在高温工艺中在金属硅化物层上几乎或不发生聚集。 因此，尽管随后的高温处理，欧姆层的薄层电阻也可能不增加。