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    RECEIVER INCLUDING OFFSET COMPENSATION CIRCUIT
    11.
    发明公开
    RECEIVER INCLUDING OFFSET COMPENSATION CIRCUIT 审中-公开

    公开(公告)号：US20230170887A1

    公开(公告)日：2023-06-01

    申请号：US17898631

    申请日：2022-08-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jueon Kim ,  Taehyoung Kim ,  Seungjin Park ,  Jihwan Hyun ,  Myoungbo Kwak ,  Junghwan Choi

    IPC: H03K5/01 ,  H03K5/24 ,  H03K5/003

    CPC classification number: H03K5/01 ,  H03K5/24 ,  H03K5/003

    Abstract: A receiver includes a differential signal generator receiving a single-ended signal, and generating differential signals having a positive signal and a negative signal based on the single-ended signal, a reference signal, and a pair of compensation signals, a pair of charging circuits charging first and second nodes to a power level in a logic low period of a clock signal, a pair of discharging circuits discharging the first and second nodes according to a level of the positive signal and a level of the negative signal, respectively, in a logic high period of the clock signal, a comparator comparing signal levels of the first and second nodes and outputting an offset detection signal of the differential signals, and an offset compensator outputting the reference signal and the pair of compensation signals, each adjusted based on the offset detection signal, to the differential signal generator.

    SEMICONDUCTOR DEVICE
    12.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250125812A1

    公开(公告)日：2025-04-17

    申请号：US18667343

    申请日：2024-05-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jejoong Woo ,  Jaewoo Park ,  Seungyeob Baek ,  Myoungbo Kwak ,  Junghwan Choi

    IPC: H03M1/00 ,  H03M1/12

    Abstract: An example semiconductor device includes a plurality of analog-to-digital converters (ADCs) configured to receive an analog signal from at least one amplifier connected to a pad, and a logic circuit configured to control the plurality of ADCs. The logic circuit is configured to activate first active ADCs, among the plurality of ADCs, in a first operating mode, and to activate second active ADCs, among the plurality of ADCs, in a second operating mode different from the first operating mode. A first latency required for the first active ADCs to receive the analog signal and to output a first digital signal is longer than a second latency required for the second active ADCs to receive the analog signal and to output a second digital signal.

    LOW DROPOUT REGULATOR AND MEMORY DEVICE INCLUDING THE SAME
    13.
    发明申请
    LOW DROPOUT REGULATOR AND MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20250060769A1

    公开(公告)日：2025-02-20

    申请号：US18760350

    申请日：2024-07-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junhan Choi ,  Jaewoo Park ,  Myoungbo Kwak ,  Jinook Jung

    IPC: G05F1/575 ,  G05F1/565 ,  G11C5/14

    Abstract: An example low dropout (LDO) regulator includes a voltage regulating circuit and an adaptive biasing circuit. The voltage regulating circuit is configured to regulate an output voltage of an output node connected with a load by using the output voltage as first feedback. The adaptive biasing circuit is configured to generate a biasing signal that supports regulation of the output voltage by using a sensing signal in an internal node of the voltage regulating circuit as second feedback, and to provide the biasing signal to the voltage regulating circuit.

    Electronic devices converting input signals to digital value and operating methods of electronic devices
    14.
    发明授权
    Electronic devices converting input signals to digital value and operating methods of electronic devices 有权

    公开(公告)号：US12176912B2

    公开(公告)日：2024-12-24

    申请号：US17974703

    申请日：2022-10-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyoungjun Roh ,  Jaewoo Park ,  Myoungbo Kwak ,  Jejoong Woo ,  Junghwan Choi

    IPC: H03M1/18 ,  H03M1/12 ,  H03M1/48 ,  H03M1/10

    Abstract: An electronic device which may include an analog-to-digital converter circuit that converts a level of an input signal to digital input values in response to a clock signal, an oscillator that generates the clock signal, a first equalization circuit that generates digital output signals by equalizing the digital input values, a first phase detector circuit that detects phases of the digital output signals and generates digital phase values, a loop filter that generates a first digital output value based on the digital phase values, a second equalization circuit that generates digital intermediate values by equalizing the digital input values, and a second phase detector circuit that detects phases of the digital intermediate values and to generate a second digital output value. The oscillator may adjust a frequency of the clock signal based on the first digital output value and the second digital output value.

    RECEIVER, OPERATION METHOD THEREOF, AND MEMORY DEVICE
    15.
    发明申请
    RECEIVER, OPERATION METHOD THEREOF, AND MEMORY DEVICE 有权

    公开(公告)号：US20240414035A1

    公开(公告)日：2024-12-12

    申请号：US18530274

    申请日：2023-12-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jueon Kim ,  Taehyoung Kim ,  Donghyun Yoon ,  Myoungbo Kwak ,  Jaewoo Park ,  Youngdon Choi ,  Junghwan Choi

    IPC: H04L25/49 ,  H04L7/033 ,  H04L25/03

    Abstract: A receiver includes a voltage-to-time converter configured to sequentially output a first converted signal and a second converted signal based on a first signal, a second signal, and a time difference; a first time comparator configured to determine a first bit value based on a first first-arrival signal (FAS) and output first data including the first bit value; a delay time generator configured to select a non-target signal and a target signal based on the first bit value and from among the first converted signal and the second converted signal; and a second time comparator configured to determine a second bit value based on a second FAS and output second data including the second bit value.

    VOLTAGE-TO-TIME CONVERTERS AND METHODS OF OPERATING SAME
    16.
    发明申请
    VOLTAGE-TO-TIME CONVERTERS AND METHODS OF OPERATING SAME 有权

    公开(公告)号：US20240413834A1

    公开(公告)日：2024-12-12

    申请号：US18597217

    申请日：2024-03-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jueon Kim ,  Taehyoung Kim ,  Donghyun Yoon ,  Myoungbo Kwak ,  Jaewoo Park ,  Youngdon Choi ,  Junghwan Choi

    IPC: H03M1/50

    Abstract: A voltage-to-time converter (VTC) includes: a first inverter electrically connected between a first node, to which a clock signal is applied, and a second node, a first buffer electrically connected to the second node and to output a first output signal, a second inverter electrically connected between a third node, to which the clock signal is applied, and a fourth node, a second buffer electrically connected to the fourth node to output a second output signal, a first linearization circuit configured to receive a first input signal and electrically connected between the first node and the second node, and a second linearization circuit configured to receive a second input signal and electrically connected between the third node and the fourth node.

    ANALOG-TO-DIGITAL CONVERSION
    18.
    发明申请
    ANALOG-TO-DIGITAL CONVERSION 有权

    公开(公告)号：US20250038754A1

    公开(公告)日：2025-01-30

    申请号：US18658820

    申请日：2024-05-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaeha Kim ,  Young Choi ,  Myoungbo Kwak ,  Jaewoo Park ,  Youngdon Choi ,  Junghwan Choi

    IPC: H03M1/06

    Abstract: The present disclosure relates to successive approximation register analog-to-digital converters. An example successive approximation register analog-to-digital converter includes a first sampling and holding circuit that samples an analog signal at a first point in time and generates a first input voltage, a second sampling and holding circuit that samples the analog signal at a second point in time and generates a second input voltage, and a first analog-to-digital converter. The first analog-to-digital converter performs a feed forward equalization function by receiving the first input voltage and the second input voltage, sampling the first input voltage and the second input voltage, and outputting a multi-bit digital signal based on a sampling result of the first input voltage and a sampling result of the second input voltage.

    RECEIVER, OPERATION METHOD THEREOF, AND MEMORY DEVICE
    20.
    发明申请
    RECEIVER, OPERATION METHOD THEREOF, AND MEMORY DEVICE 有权

    公开(公告)号：US20240412764A1

    公开(公告)日：2024-12-12

    申请号：US18419959

    申请日：2024-01-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jueon Kim ,  Taehyoung Kim ,  Donghyun Yoon ,  Myoungbo Kwak ,  Jaewoo Park ,  Youngdon Choi ,  Junghwan Choi

    IPC: G11C7/10 ,  G11C7/22

    Abstract: A receiver includes a decoding circuit configured to convert a data signal into first and second signals having a time difference therebetween, which is a function of at least one parameter, and output decoded data based on the first signal and the second signal. A calibration circuit is provided, which is configured to calibrate a value of the at least one parameter based on one of the first signal and the second signal, and a reference timing signal, and provide a calibration signal including the calibrated value to the decoding circuit. The reference timing signal may have a reference timing that sets a ratio between a first probability and a second probability as an integer ratio.

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