公开(公告)号：US20220384623A1

公开(公告)日：2022-12-01

申请号：US17886612

申请日：2022-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil KANG ,  Dongwon KIM ,  Minyi KIM ,  Keun Hwi CHO

IPC: H01L29/732 ,  H01L21/8228 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/735

Abstract: A semiconductor device including a well region in a substrate, an impurity region in the well region, a first active fin on the impurity region, a second active fin on the well region, and a connection pattern penetrating the second active fin and connected to the well region may be provided. The substrate and the impurity region include impurities having a first conductivity type. The well region includes impurities having a second conductivity type different from the first conductivity type. The first active fin includes a plurality of first semiconductor patterns that are spaced apart from each other in a direction perpendicular to a top surface of the substrate. The first semiconductor patterns and the impurity region include impurities having the first conductivity type.

公开(公告)号：US20220246601A1

公开(公告)日：2022-08-04

申请号：US17720153

申请日：2022-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon BAEK ,  Myung Gil KANG ,  Jae-Ho PARK ,  Seung Young LEE

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L27/118

Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.

公开(公告)号：US20220130865A1

公开(公告)日：2022-04-28

申请号：US17336785

申请日：2021-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beom Jin PARK ,  Myung Gil KANG ,  Dong Won KIM ,  Keun Hwi CHO

IPC: H01L27/12 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L21/84 ,  H01L29/66

Abstract: A semiconductor device that reduces the occurrence of a leakage current by forming a doped layer in each of an NMOS region and a PMOS region on an SOT substrate, and completely separating the doped layer of the NMOS region from the doped layer of the PMOS region using the element isolation layer is provided. The semiconductor device includes a first region and a second region adjacent to the first region, a substrate including a first layer, an insulating layer on the first layer, and a second layer on the insulating layer, a first doped layer on the second layer in the first region and including a first impurity, a second doped layer on the second layer in the second region and including a second impurity different from the first impurity, and an element isolation layer configured to separate the first doped layer from the second doped layer, and in contact with the insulating layer.

公开(公告)号：US20210074697A1

公开(公告)日：2021-03-11

申请号：US16842053

申请日：2020-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon BAEK ,  Myung Gil KANG ,  Jae-Ho PARK ,  Seung Young LEE

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.

公开(公告)号：US20200219879A1

公开(公告)日：2020-07-09

申请号：US16439999

申请日：2019-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Cheol SHIN ,  Myung Gil KANG ,  Sadaaki MASUOKA ,  Sang Hoo LEE ,  Sung Man WHANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  H01L21/8238 ,  H01L21/02

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

公开(公告)号：US20240355883A1

公开(公告)日：2024-10-24

申请号：US18385537

申请日：2023-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyumin YOO ,  Myung Gil KANG ,  Dongwon KIM ,  Jongsu KIM ,  Beomjin PARK ,  Byeonghee SON

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0847 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/0653

Abstract: A semiconductor device includes a substrate including an active pattern; a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns, which are stacked to be spaced apart from each other; a source/drain pattern connected to the plurality of semiconductor patterns; a gate electrode on the plurality of semiconductor patterns; and a blocking layer between the source/drain pattern and the active pattern, wherein the source/drain pattern includes a protruding side surface protruding toward the semiconductor patterns, the blocking layer includes silicon-germanium (SiGe), and a germanium concentration of the blocking layer is higher than a germanium concentration of the source/drain pattern.

公开(公告)号：US20240178293A1

公开(公告)日：2024-05-30

申请号：US18228824

申请日：2023-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyumin YOO ,  Beomjin PARK ,  Myung Gil KANG ,  Dongwon KIM ,  Younggwon KIM

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/7848

Abstract: Disclosed is a semiconductor device comprising a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns spaced apart from and vertically stacked on each other, a source/drain pattern connected to the semiconductor patterns having a p-type, a gate electrode on the semiconductor patterns and including inner electrodes between neighboring semiconductor patterns and an outer electrode on an uppermost semiconductor pattern, and a gate dielectric layer between the gate electrode and the semiconductor patterns and including an inner gate dielectric layer adjacent to the inner electrode and an outer gate dielectric layer that extends from bottom to lateral surfaces of the outer electrode. The outer electrode and the outer gate dielectric layer have an inverted T shape.

公开(公告)号：US20240096894A1

公开(公告)日：2024-03-21

申请号：US18521253

申请日：2023-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Cheol SHIN ,  Myung Gil KANG ,  Sadaaki MASUOKA ,  Sang Hoon LEE ,  Sung Man WHANG

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

公开(公告)号：US20240030304A1

公开(公告)日：2024-01-25

申请号：US18478373

申请日：2023-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon KIM ,  Myung Gil KANG ,  Wandon KIM

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/42364 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/78696

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The device may include a substrate, an active pattern in an upper portion of the substrate and is extending in a first direction, a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction, a first gate spacer covering a side surface of the gate electrode, a first inhibition layer between the gate electrode and the first gate spacer, and a gate insulating layer between the gate electrode and the active pattern. The gate insulating layer may include a high-k dielectric layer and a gate oxide layer. The gate oxide layer may be between the high-k dielectric layer and the active pattern. The high-k dielectric layer may be between the gate oxide layer and the gate electrode.

公开(公告)号：US20240006497A1

公开(公告)日：2024-01-04

申请号：US18138877

申请日：2023-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo Jin JEONG ,  Myung Gil KANG ,  Tae Gon KIM ,  Dong Won KIM ,  Ju Ri LEE

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/41775 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66545

Abstract: A semiconductor device includes an active pattern having a lower pattern, and a plurality of sheet patterns spaced apart from the lower pattern in a first direction; first and second structures disposed on the lower pattern, wherein the first and second structures are arranged and spaced apart from each other in a second direction; a source/drain recess defined between first and second gate structures; and a source/drain pattern filling the source/drain recess, wherein the source/drain pattern includes a stacking fault spaced apart from the lower pattern.