公开(公告)号：US10170549B2

公开(公告)日：2019-01-01

申请号：US14918954

申请日：2015-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  H01L29/778

Abstract: Exemplary embodiments provide for fabricating a nanosheet stack structure having one or more sub-stacks. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial stack of one or more sub-stacks, each of the sub-stacks having at least three layers, a sacrificial layer A, and at least two different non-sacrificial layers B and C having different material properties, wherein the non-sacrificial layers B and C layers are kept below a thermodynamic or kinetic critical thickness corresponding to metastability during all processing, and wherein the sacrificial layer An is placed only at a top or a bottom of each of the sub-stacks, and each of the sub-stacks is connected to an adjacent sub-stack at the top or the bottom using one of the sacrificial layers A; proceeding with fabrication flow of nanosheet devices, such that pillar structures are formed at each end of the epitaxial crystalline stack that to hold the nanosheets in place after selective etch of the sacrificial layers; and selectively removing sacrificial layers A to all non-sacrificial layers B and C, while the remaining layers in the stack are held in place by the pillar structures so that after removal of the sacrificial layers An, each of the sub-stacks contains the non-sacrificial layers B and C.

公开(公告)号：US09685509B2

公开(公告)日：2017-06-20

申请号：US14226518

申请日：2014-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Mark S. Rodder ,  Robert C. Bowen

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/086 ,  H01L29/0878 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/785

Abstract: A finFET device can include a high mobility semiconductor material in a fin structure that can provide a channel region for the finFET device. A source/drain recess can be adjacent to the fin structure and a graded composition epi-grown semiconductor alloy material, that includes a component of the high mobility semiconductor material, can be located in the source/drain recess.

公开(公告)号：US09613907B2

公开(公告)日：2017-04-04

申请号：US14809266

申请日：2015-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ganesh Hegde ,  Mark S. Rodder ,  Jorge A. Kittl ,  Robert C. Bowen

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A damascene interconnect structure may be formed by forming a trench in an ILD. A diffusion barrier may be deposited on trench surfaces, followed by a first liner material. The first liner material may be removed from a bottom surface of the trench. A second liner material may be directionally deposited on the bottom. A conductive seed layer may be deposited on the first and second liner materials, and a conductive material may fill in the trench. A CMP process can remove excess material from the top of the structure. A damascene interconnect may include a dielectric having a trench, a first liner layer arranged on trench sidewalls, and a second liner layer arranged on a trench bottom. A conductive material may fill the trench. The first liner material may have low wettability and the second liner material may have high wettability with respect to the conductive material.

公开(公告)号：US20160071729A1

公开(公告)日：2016-03-10

申请号：US14830622

申请日：2015-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Robert C. Bowen ,  Wei-E Wang ,  Mark S. Rodder

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/1033 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02474 ,  H01L21/02477 ,  H01L21/02483 ,  H01L21/02485 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02538 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78696

Abstract: Exemplary embodiments provide methods for fabricating a nanosheet structure suitable for field-effect transistor (FET) fabrication. Aspects of exemplary embodiment include selecting an active material that will serve as a channel material in the nanosheet structure, a substrate suitable for epitaxial growth of the active material, and a sacrificial material to be used during fabrication of the nanosheet structure; growing a stack of alternating layers of active and sacrificial materials over the substrate; and selectively etching the sacrificial material, wherein due to the properties of the sacrificial material, the selective etch results in remaining layers of active material having an aspect ratio greater than 1 and substantially a same thickness and atomic smoothness along the entire cross-sectional width of each active material layer perpendicular to current flow.

Abstract translation: 示例性实施例提供了制造适用于场效应晶体管（FET）制造的纳米片结构的方法。 示例性实施方案的方面包括选择将用作纳米片结构中的通道材料的活性材料，适于活性材料的外延生长的基底和在纳米片结构的制造期间使用的牺牲材料; 在衬底上生长一叠交替的活性和牺牲材料层; 并且选择性地蚀刻牺牲材料，其中由于牺牲材料的性质，选择性蚀刻导致活性材料的剩余层具有大于1的纵横比和基本上相同的厚度和原子平滑度沿着整个横截面宽度 每个活性物质层垂直于电流。

公开(公告)号：US09583590B2

公开(公告)日：2017-02-28

申请号：US14698402

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

IPC: H01L29/66 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/308 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66522 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Methods of forming a finFET are provided. The methods may include forming a fin-shaped channel region including indium (In) on a substrate, forming a deep source/drain region adjacent to the channel region on the substrate and forming a source/drain extension region between the channel region and the deep source/drain region. Opposing sidewalls of the source/drain extension region may contact the channel region and the deep source/drain region, respectively, and the source/drain extension region may include InyGa1−yAs, and y is in a range of about 0.3 to about 0.5.

Abstract translation: 提供了形成finFET的方法。 所述方法可以包括在衬底上形成包括铟（In）的鳍状沟道区域，形成与衬底上的沟道区相邻的深源极/漏极区域，并在沟道区域和深度之间形成源极/漏极延伸区域 源/漏区。 源极/漏极延伸区域的相对侧壁可以分别接触沟道区域和深源极/漏极区域，并且源极/漏极延伸区域可以包括In y Ga 1-y As，y在约0.3至约0.5的范围内。

公开(公告)号：US09525053B2

公开(公告)日：2016-12-20

申请号：US14304008

申请日：2014-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Mark S. Rodder ,  Robert C. Bowen ,  Jorge A. Kittl

IPC: H01L29/04 ,  H01L29/778 ,  H01L29/12 ,  H01L29/78 ,  H01L29/267 ,  H01L29/66 ,  H01L29/06 ,  H01L29/22

CPC classification number: H01L29/7781 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/122 ,  H01L29/22 ,  H01L29/267 ,  H01L29/66431 ,  H01L29/785

Abstract: Integrated circuit devices including strained channel regions and methods of forming the same are provided. The integrated circuit devices may include enhancement-mode field effect transistors. The enhancement-mode field effect transistors may include a quantum well channel region having a well thickness Tw sufficient to yield a strain-induced splitting of a plurality of equivalent-type electron conduction states therein to respective unequal energy levels including a lowermost energy level associated with a lowermost surface roughness scattering adjacent a surface of the channel region when, the surface is biased into a state of inversion.

Abstract translation: 提供包括应变通道区域的集成电路器件及其形成方法。 集成电路器件可以包括增强型场效应晶体管。 增强型场效应晶体管可以包括具有足够的阱厚度Tw的量子阱沟道区，其足以产生其中的多个等效型电子传导状态的应变引起的分裂到相应的不等能级，包括与 当表面被偏置到反转状态时，邻近通道区域的表面的最低表面粗糙度散射。

公开(公告)号：US20160111284A1

公开(公告)日：2016-04-21

申请号：US14918954

申请日：2015-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L21/283 ,  H01L21/306

CPC classification number: H01L29/0669 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L29/0665 ,  H01L29/1054 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7783

Abstract: Exemplary embodiments provide for fabricating a nanosheet stack structure having one or more sub-stacks. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial stack of one or more sub-stacks, each of the sub-stacks having at least three layers, a sacrificial layer A, and at least two different non-sacrificial layers B and C having different material properties, wherein the non-sacrificial layers B and C layers are kept below a thermodynamic or kinetic critical thickness corresponding to metastability during all processing, and wherein the sacrificial layer An is placed only at a top or a bottom of each of the sub-stacks, and each of the sub-stacks is connected to an adjacent sub-stack at the top or the bottom using one of the sacrificial layers A; proceeding with fabrication flow of nanosheet devices, such that pillar structures are formed at each end of the epitaxial crystalline stack that to hold the nanosheets in place after selective etch of the sacrificial layers; and selectively removing sacrificial layers A to all non-sacrificial layers B and C, while the remaining layers in the stack are held in place by the pillar structures so that after removal of the sacrificial layers An, each of the sub-stacks contains the non-sacrificial layers B and C.

Abstract translation: 示例性实施例提供制造具有一个或多个子堆叠的纳米片堆叠结构。 示例性实施例的方面包括：生长一个或多个子堆叠的外延晶体初始堆叠，每个子堆叠具有至少三个层，牺牲层A和至少两个不同的非牺牲层B和C 具有不同的材料性质，其中非牺牲层B和C层保持低于在所有加工期间对应于亚稳态的热力学或动力学临界厚度，并且其中牺牲层An仅被放置在每个的顶部或底部 并且每个子堆叠使用牺牲层A之一连接到顶部或底部的相邻子堆叠; 继续纳米片装置的制造流程，使得在外延晶体堆叠的每个端部处形成柱结构，以在选择性蚀刻牺牲层之后将纳米片保持在适当位置; 并且将牺牲层A选择性地去除所有非牺牲层B和C，而堆叠中的其余层被柱结构保持就位，使得在去除牺牲层An之后，每个子堆包含非牺牲层 - 层B和C.

公开(公告)号：US09236444B2

公开(公告)日：2016-01-12

申请号：US13947239

申请日：2013-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Robert C. Bowen

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66469 ,  H01L29/66795 ,  H01L29/7784 ,  H01L29/785

Abstract: Methods of fabricating quantum well field effect transistors are provided. The methods may include forming a first barrier layer including a first delta doped layer on a quantum well layer and forming a second barrier layer including a second delta doped layer selectively on a portion of the first barrier layer in a first region of the substrate. The methods may also include patterning the first and second barrier layers and the quantum well layer to form a first quantum well channel structure in the first region and patterning the first barrier layer and the quantum well layer to form a second quantum well channel structure in a second region. The methods may further include forming a gate insulating layer on the first and second quantum well channel structures of the substrate and forming a gate electrode layer on the gate insulating layer.

Abstract translation: 提供了量子阱场效应晶体管的制造方法。 所述方法可以包括在量子阱层上形成包括第一δ掺杂层的第一势垒层，并且在衬底的第一区域中在第一势垒层的一部分上选择性地形成包括第二δ掺杂层的第二阻挡层。 所述方法还可以包括图案化第一和第二阻挡层和量子阱层，以在第一区域中形成第一量子阱沟道结构，并且对第一势垒层和量子阱层进行构图以形成第二量子阱沟道结构 第二区。 该方法还可以包括在衬底的第一和第二量子阱沟道结构上形成栅极绝缘层，并在栅极绝缘层上形成栅极电极层。

公开(公告)号：US09112130B2

公开(公告)日：2015-08-18

申请号：US14478344

申请日：2014-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Robert C. Bowen

IPC: H03K19/195 ,  H01L49/00 ,  H01L29/16 ,  H01L29/20 ,  H01L29/88 ,  H01L29/06

CPC classification number: H01L49/006 ,  H01L29/0669 ,  H01L29/1606 ,  H01L29/20 ,  H01L29/88

Abstract: A logic device is provided which includes an electron monochromator. The electron monochromator includes a quantum dot disposed between first and second tunneling barriers, an emitter coupled to the first tunneling barrier, and a collector coupled to the second tunneling barrier. The logic device also includes a quantum interference device. The quantum interference device includes a source which is coupled to the collector of the electron monochromator.

Abstract translation: 提供了一种包括电子单色仪的逻辑器件。 电子单色仪包括设置在第一和第二隧道势垒之间的量子点，耦合到第一隧道势垒的发射极和耦合到第二隧穿势垒的集电极。 逻辑器件还包括量子干涉器件。 量子干涉装置包括耦合到电子单色仪的集电极的源。

公开(公告)号：US20150123701A1

公开(公告)日：2015-05-07

申请号：US14478344

申请日：2014-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Robert C. Bowen

IPC: H01L49/00 ,  H01L29/06 ,  H01L29/88 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L49/006 ,  H01L29/0669 ,  H01L29/1606 ,  H01L29/20 ,  H01L29/88

Abstract: A logic device is provided which includes an electron monochromator. The electron monochromator includes a quantum dot disposed between first and second tunneling barriers, an emitter coupled to the first tunneling barrier, and a collector coupled to the second tunneling barrier. The logic device also includes a quantum interference device. The quantum interference device includes a source which is coupled to the collector of the electron monochromator.

Abstract translation: 提供了一种包括电子单色仪的逻辑器件。 电子单色仪包括设置在第一和第二隧道势垒之间的量子点，耦合到第一隧道势垒的发射极和耦合到第二隧穿势垒的集电极。 逻辑器件还包括量子干涉器件。 量子干涉装置包括耦合到电子单色仪的集电极的源。