公开(公告)号：US09171825B2

公开(公告)日：2015-10-27

申请号：US14488707

申请日：2014-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Sick Park ,  In-Young Lee ,  Byoung-Soo Kwak ,  Min-Soo Kim ,  Sang-Wook Park ,  Tae-Je Cho

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49816 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/94 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2924/00

Abstract: A semiconductor device and a method of fabricating the same includes providing a first semiconductor chip which has first connection terminals, providing a second semiconductor chip which comprises top and bottom surfaces facing each other and has second connection terminals and a film-type first underfill material formed on the bottom surface thereof, bonding the first semiconductor chip to a mounting substrate by using the first connection terminals, bonding the first semiconductor chip and the second semiconductor chip by using the first underfill material, and forming a second underfill material which fills a space between the mounting substrate and the first semiconductor chip and covers side surfaces of the first semiconductor chip and at least part of side surfaces of the second semiconductor chip.

Abstract translation: 一种半导体器件及其制造方法包括提供具有第一连接端子的第一半导体芯片，提供第二半导体芯片，该第二半导体芯片包括彼此相对的顶表面和底表面，并且具有第二连接端子和形成的膜型第一底部填充材料 在其底面上，通过使用第一连接端子将第一半导体芯片接合到安装基板，通过使用第一底部填充材料接合第一半导体芯片和第二半导体芯片，以及形成填充第二底部填充材料之间的空间的第二底部填充材料 安装基板和第一半导体芯片，并且覆盖第一半导体芯片的侧表面和第二半导体芯片的至少一部分侧表面。

公开(公告)号：US20140299980A1

公开(公告)日：2014-10-09

申请号：US14160008

申请日：2014-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Kyoung Choi ,  Jong-Youn Kim ,  Sang-Wook Park ,  Hae-Jung Yu ,  In-Young Lee ,  Sang-Uk Han ,  Ji-Seok Hong

IPC: H01L23/522 ,  H01L23/34

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3737 ,  H01L23/4334 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: Semiconductor packages including a heat spreader and methods of forming the same are provided. The semiconductor packages may include a first semiconductor chip, a second semiconductor chip, and a heat spreader stacked sequentially. The semiconductor packages may also include a thermal interface material (TIM) layer surrounding the second semiconductor chip and directly contacting a sidewall of the second semiconductor chip. An upper surface of the TIM layer may directly contact a lower surface of the heat spreader, and a sidewall of the TIM layer may be substantially coplanar with a sidewall of the heat spreader. In some embodiments, a sidewall of the first semiconductor chip may be substantially coplanar with the sidewall of the TIM layer.

Abstract translation: 提供了包括散热器的半导体封装及其形成方法。 半导体封装可以包括顺序堆叠的第一半导体芯片，第二半导体芯片和散热器。 半导体封装还可以包括围绕第二半导体芯片并直接接触第二半导体芯片的侧壁的热界面材料（TIM）层。 TIM层的上表面可以直接接触散热器的下表面，并且TIM层的侧壁可以与散热器的侧壁基本上共面。 在一些实施例中，第一半导体芯片的侧壁可以与TIM层的侧壁基本共面。

公开(公告)号：US08648408B2

公开(公告)日：2014-02-11

申请号：US13753588

申请日：2013-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Kuk Jeong ,  Sang-Wook Park ,  Min-Hee Choi

IPC: H01L21/02

CPC classification number: H01L29/7831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/823807 ,  H01L21/8258 ,  H01L23/291 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, a gate structure disposed on the substrate and which includes a gate insulating layer and a gate electrode layer, a first nitride layer disposed on the substrate and the gate structure and which includes silicon, and a second nitride layer that is disposed on the first nitride layer and has an atomic percentage of silicon less than that of the first nitride layer.

Abstract translation: 半导体器件包括衬底，设置在衬底上的栅极结构，其包括栅极绝缘层和栅极电极层，设置在衬底上的第一氮化物层和栅极结构，并且包括硅;以及第二氮化物层， 设置在第一氮化物层上，并且硅的原子百分比小于第一氮化物层的原子百分比。