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    THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    11.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20250024691A1

    公开(公告)日：2025-01-16

    申请号：US18417937

    申请日：2024-01-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngsun SONG ,  Seulji Song ,  Bon Jae Koo

    IPC: H10B99/00

    Abstract: A three-dimensional memory device includes a base dielectric layer disposed on a substrate, a stack structure that includes word lines and interlayer dielectric layers that are alternately stacked on the base dielectric layer, a bit line that penetrates the stack structure and extends in a vertical direction perpendicular to a top surface of the substrate, and buried storage patterns interposed between the bit line and the word lines and spaced apart from each other in the vertical direction. Each of the buried storage patterns has a width in a horizontal direction parallel to the top surface of the substrate. The widths of the buried storage patterns increase with increasing vertical distance from the substrate.

    Variable resistance memory devices and methods of forming the same
    12.
    发明授权
    Variable resistance memory devices and methods of forming the same 有权

    公开(公告)号：US10714686B2

    公开(公告)日：2020-07-14

    申请号：US15869892

    申请日：2018-01-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungwon Kim ,  Sung-Ho Eun ,  Ilmok Park ,  Junghoon Park ,  Seulji Song ,  Ji-Hyun Jeong

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    Abstract: Variable resistance memory devices and methods of forming the same are provided. The variable resistance memory devices may include a substrate including a cell region and a peripheral region, first conductive lines on the substrate, second conductive lines traversing the first conductive lines, variable resistance structures at intersecting points of the first conductive lines and the second conductive lines, and bottom electrodes between the first conductive lines and the variable resistance structures. The cell region may include a boundary region contacting the peripheral region, and one of the first conductive lines is electrically insulated from one of the variable resistance structures that is on the boundary region and overlaps the one of the first conductive lines.

    SEMICONDUCTOR DEVICES
    14.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20250157934A1

    公开(公告)日：2025-05-15

    申请号：US18918467

    申请日：2024-10-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Suhyun Bang ,  Seulji Song ,  Hwayeong Lee

    IPC: H01L23/532 ,  H10B12/00

    Abstract: A semiconductor device includes a bit line above a substrate and extending in a first horizontal direction, a word line at a higher vertical level than the bit line and extending in a second horizontal direction crossing the first horizontal direction, a fluorine-containing insulating layer spaced apart from the word line and extending in the second horizontal direction, and a channel layer between the word line and the fluorine-containing insulating layer, the channel layer including a first side surface and a second side surface opposite to the first side surface. The first side surface faces the word line, and the channel layer includes an oxide semiconductor and fluorine.

    MEMORY DEVICE INCLUDING SWITCHING PATTERN
    15.
    发明申请
    MEMORY DEVICE INCLUDING SWITCHING PATTERN 有权

    公开(公告)号：US20250056814A1

    公开(公告)日：2025-02-13

    申请号：US18796880

    申请日：2024-08-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seulji Song ,  Hodae Kim ,  Woojun Jeong

    IPC: H10B63/00 ,  H10N70/00

    Abstract: A memory device includes a first conductive line, a second conductive line, and a memory cell disposed between the first and second conductive lines. The memory cell includes a lower electrode layer, a switching pattern, and an upper electrode layer. The switching pattern includes a main region including a pair of first side walls and a pair of second walls, and a corner region at four corners of the main region. The switching pattern includes a chalcogenide layer including a Group VI chalcogen element, an element of Group IV and an element of Group V, and the concentration of the Group IV element in the corner region is greater than that of the Group IV element in the main region, or the concentration of the Group V element in the corner region is greater than that of the Group V element in the main region.

    SEMICONDUCTOR MEMORY DEVICES
    17.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20250048655A1

    公开(公告)日：2025-02-06

    申请号：US18737537

    申请日：2024-06-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Bonjae KOO ,  Seulji Song ,  Youngsun Song

    IPC: H10B99/00

    Abstract: Provided is a semiconductor memory device including: cell blocks, each including a folding structure in which electrode structures and insulating structures are alternately provided, wherein the electrode structures and the insulating structures extend in a vertical direction and are connected with each other so as to have at least two U-shaped structures forming villus shapes in a plan view, the electrode structures include a vertical electrode and a switching material layer, and the cell blocks are provided in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction; and a gate stack structure including gate electrodes and interlayer insulating layers that are alternately stacked in the vertical direction along sidewalls of the electrode structures.

    MEMORY DEVICES INCLUDING FERROELECTRIC CELL CAPACITORS AND OPERATING METHODS THEREOF
    19.
    发明申请
    MEMORY DEVICES INCLUDING FERROELECTRIC CELL CAPACITORS AND OPERATING METHODS THEREOF 有权

    公开(公告)号：US20250054532A1

    公开(公告)日：2025-02-13

    申请号：US18797698

    申请日：2024-08-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hwayeong Lee ,  Seulji Song

    IPC: G11C11/22

    Abstract: A memory device including a ferroelectric cell capacitor, and an operating method thereof. For example, an operating method of a memory device, according to some embodiments, may include pre-charging a bit line to a pre-charge voltage, the bit line connected to a ferroelectric cell capacitor to be written to, writing data into the ferroelectric cell capacitor by adjusting a level of a voltage applied to a bit line and a word line corresponding to the ferroelectric cell capacitor, and deactivating the word line, wherein a voltage applied to a plate line connected to the ferroelectric cell capacitor is maintained at a ground voltage during the writing of the data into the ferroelectric cell capacitor.

    SEMICONDUCTOR MEMORY DEVICE
    20.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20250040145A1

    公开(公告)日：2025-01-30

    申请号：US18786011

    申请日：2024-07-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Bonjae KOO ,  Seulji Song ,  Youngsun Song

    IPC: H10B51/20 ,  H01L29/78 ,  H10B51/10 ,  H10B51/40

    Abstract: A semiconductor memory device is provided. The semiconductor device includes: a stacked structure with word line plates and mold insulating layers which extend in first and second horizontal directions, and are alternately stacked in a vertical direction in a cell array region and an extension region, the plurality of word line plates forming a staircase structure in the extension region; a vertical bit line extending into the stacked structure in the cell array region; a plurality of selection layers between the plurality of word line plates and the vertical bit line; and a vertical channel transistor connected to one end of the vertical bit line. A first thickness of each of the plurality of mold insulating layers is about 1.5 times to about 3 times a second thickness of each of the plurality of word line plates.

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