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公开(公告)号：US09768232B2
公开(公告)日：2017-09-19
申请号：US15297687
申请日：2016-10-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Ho Eun
IPC: H01L45/00 , H01L27/24 , H01L23/528
CPC classification number: H01L27/2463 , H01L23/528 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1683 , H01L45/1691
Abstract: A variable resistance memory device including a substrate, a first insulation layer disposed on the substrate, first and second conductive lines, and memory units. The first conductive lines are arranged in a first direction on the first insulation layer and extend in a second direction. The second conductive lines are disposed over the first conductive lines, are arranged in the second direction, and extend in the first direction. The memory units are disposed in each area between the first and second conductive lines in a third direction and include a first electrode, a variable resistance pattern, a selection pattern, and a second electrode. The first electrode and the variable resistance pattern include a cross-section having an “L” shape. The variable resistance pattern contacts an upper surface of the first electrode. The second electrode is disposed on the variable resistance pattern. The selection pattern is disposed on the second electrode.
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Patent Agency Ranking
公开(公告)号：US11227991B2
公开(公告)日：2022-01-18
申请号：US16916227
申请日：2020-06-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Jun Seong , Sung-Ho Eun , Soon-Oh Park
Abstract: A semiconductor memory device includes first conductive lines extending in a first direction on a substrate, second conductive lines extending in a second direction over the first conductive line, the first and the second conductive lines crossing each other at cross points, a cell structure positioned at each of the cross points, each of the cell structures having a data storage element, a selection element to apply a cell selection signal to the data storage element and to change a data state of the data storage element, and an electrode element having at least an electrode with a contact area smaller than that of the selection element, and an insulation pattern insulating the first and the second conductive lines and the cell structures from one another.
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公开(公告)号：US10714686B2
公开(公告)日：2020-07-14
申请号：US15869892
申请日：2018-01-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungwon Kim , Sung-Ho Eun , Ilmok Park , Junghoon Park , Seulji Song , Ji-Hyun Jeong
Abstract: Variable resistance memory devices and methods of forming the same are provided. The variable resistance memory devices may include a substrate including a cell region and a peripheral region, first conductive lines on the substrate, second conductive lines traversing the first conductive lines, variable resistance structures at intersecting points of the first conductive lines and the second conductive lines, and bottom electrodes between the first conductive lines and the variable resistance structures. The cell region may include a boundary region contacting the peripheral region, and one of the first conductive lines is electrically insulated from one of the variable resistance structures that is on the boundary region and overlaps the one of the first conductive lines.
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公开(公告)号：US10971548B2
公开(公告)日：2021-04-06
申请号：US16354545
申请日：2019-03-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Ho Eun , Daehwan Kang , Sungwon Kim , Youngbae Kim , Seokjae Won
Abstract: A variable resistance non-volatile memory device can include a semiconductor substrate and a plurality of first conductive lines each extending in a first direction perpendicular to the semiconductor substrate and spaced apart in a second direction on the semiconductor substrate. A second conductive line can extend in the second direction parallel to the semiconductor substrate on a first side of the plurality of first conductive lines and a third conductive line can extend in the second direction parallel to the semiconductor substrate on a second side of the plurality of first conductive lines opposite the first side of the plurality of first conductive lines. A plurality of first non-volatile memory cells can be on the first side of the plurality of first conductive lines and each can be coupled to the second conductive line and to a respective one of the plurality of first conductive lines, where each of the plurality of first non-volatile memory cells can include a switching element, a variable resistance element, and an electrode arranged in a first sequence. A plurality of second non-volatile memory cells can be on the second side of the plurality of first conductive lines and each can be coupled to the third conductive line and to a respective one of the plurality of first conductive lines, wherein each of the plurality of second non-volatile memory cells includes a switching element, a variable resistance element, and an electrode that are arranged in a second sequence, wherein the first sequence and the second sequence are symmetrical with one another about the plurality of first conductive lines.
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公开(公告)号：US20190019950A1
公开(公告)日：2019-01-17
申请号：US15869892
申请日：2018-01-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungwon Kim , Sung-Ho Eun , Ilmok Park , Junghoon Park , Seulji Song , Ji-Hyun Jeong
CPC classification number: H01L45/1675 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C2213/31 , G11C2213/76 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/122 , H01L45/1233 , H01L45/1273 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1683 , H01L45/1691
Abstract: Variable resistance memory devices and methods of forming the same are provided. The variable resistance memory devices may include a substrate including a cell region and a peripheral region, first conductive lines on the substrate, second conductive lines traversing the first conductive lines, variable resistance structures at intersecting points of the first conductive lines and the second conductive lines, and bottom electrodes between the first conductive lines and the variable resistance structures. The cell region may include a boundary region contacting the peripheral region, and one of the first conductive lines is electrically insulated from one of the variable resistance structures that is on the boundary region and overlaps the one of the first conductive lines,
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公开(公告)号：US09559147B2
公开(公告)日：2017-01-31
申请号：US15083639
申请日：2016-03-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Ho Eun
CPC classification number: H01L27/2463 , H01L23/528 , H01L27/224 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
Abstract: A semiconductor device includes first conductive lines and first and second insulation patterns on a substrate, first structures spaced apart from each other on the first conductive lines, a variable resistance pattern on the first structures, and a second electrode on the variable resistance pattern. The first conductive lines extend in a first direction. The first structures include a switching pattern and a first electrode sequentially stacked. The first insulation pattern fills a space between the first structures in a second direction and the first insulation pattern has a first top surface higher than a top surface of the first structures. The second insulation pattern fills a space between the first structures in the first direction, and the second insulation pattern has a second top surface higher than a top surface of the first structures. The variable resistance pattern fills an opening defined by the first and second insulation patterns.
Abstract translation: 半导体器件包括第一导电线以及衬底上的第一和第二绝缘图案，在第一导电线上彼此间隔开的第一结构，第一结构上的可变电阻图案，以及可变电阻图案上的第二电极。 第一导线沿第一方向延伸。 第一结构包括顺序层叠的开关图案和第一电极。 第一绝缘图案在第二方向上填充第一结构之间的空间，并且第一绝缘图案具有高于第一结构的顶表面的第一顶表面。 第二绝缘图案在第一方向上填充第一结构之间的空间，并且第二绝缘图案具有比第一结构的顶表面高的第二顶表面。 可变电阻图案填充由第一和第二绝缘图案限定的开口。
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