公开(公告)号：US20140357035A1

公开(公告)日：2014-12-04

申请号：US14460081

申请日：2014-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shigenobu MAEDA ,  Hyun-pil NOH ,  Choong-ho LEE ,  Seog-heon HAM

IPC: H01L21/8236 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/8236 ,  H01L21/77 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823857 ,  H01L25/00 ,  H01L27/00 ,  H01L27/0883 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device including a high voltage transistor and a low voltage transistor and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate including a high voltage region and a low voltage region; a high voltage transistor formed in the high voltage region and including a first active region, a first source/drain region, a first gate insulating layer, and a first gate electrode; and a low voltage transistor formed in the low voltage region and including a second active region, a second source/drain region, a second gate insulating layer, and a second gate electrode. The second source/drain region has a smaller thickness than a thickness of the first source/drain region.

Abstract translation: 提供了包括高压晶体管和低压晶体管的半导体器件及其制造方法。 半导体器件包括：包括高电压区域和低电压区域的半导体衬底; 形成在高电压区域中并包括第一有源区，第一源极/漏极区，第一栅极绝缘层和第一栅电极的高压晶体管; 以及形成在所述低电压区域中并包括第二有源区，第二源极/漏极区，第二栅极绝缘层和第二栅电极的低电压晶体管。 第二源极/漏极区域的厚度小于第一源极/漏极区域的厚度。

公开(公告)号：US20240324192A1

公开(公告)日：2024-09-26

申请号：US18613868

申请日：2024-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Young LEE ,  Shigenobu MAEDA ,  Kwan Young KIM ,  Bora KIM ,  Hoonjin BANG ,  Sangjin LEE

IPC: H10B20/25

CPC classification number: H10B20/25

Abstract: A one-time programmable (OTP) memory device includes: a semiconductor substrate having a write region and a read region; write gates disposed in the write region of the semiconductor substrate; read gates disposed in the read region of the semiconductor substrate; source/drain regions arranged adjacent to the write gates and the read gates and arranged in the semiconductor substrate; and a device isolation layer located between the write gates and arranged in the semiconductor substrate, wherein, in the semiconductor substrate, channel regions located below the write gates have a first conductivity type, wherein the source/drain regions have a second conductivity type, different from the first conductivity type, and wherein a pocket well is formed in the write region of the semiconductor substrate and has the second conductivity type.

公开(公告)号：US20240274453A1

公开(公告)日：2024-08-15

申请号：US18440649

申请日：2024-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhong YUN ,  Shigenobu MAEDA ,  Kyungtae KIM ,  Donghyun KIM ,  Sangyoon PARK

IPC: H01L21/67 ,  G05B13/02

CPC classification number: H01L21/67288 ,  G05B13/027 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/67276

Abstract: A semiconductor production system includes: a first chamber that is configured to be set to a first setting value and process wafers; a second chamber that is configured to be set to a second setting value and process the wafers processed in the first chamber; and a fault detection and classification (FDC) modeling module configured to: train a first FDC machine learning model to generate, based on the first setting value and first FDC values sensed with respect to the wafers processed in the first chamber, first predicted FDC values with respect to first virtual wafers in the first chamber; and train a second FDC machine learning model to generate, based on the second setting value and second FDC values sensed with respect to the wafers processed in the second chamber, second predicted FDC values with respect to second virtual wafers in the second chamber.

公开(公告)号：US20200286999A1

公开(公告)日：2020-09-10

申请号：US16881133

申请日：2020-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Shigenobu MAEDA ,  Seunghan SEO ,  Yeohyun SUNG

IPC: H01L29/16 ,  H01L29/165 ,  H01L29/267 ,  H01L29/778 ,  H01L29/786 ,  H01L29/24 ,  H01L29/66 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/20 ,  H01L29/22 ,  H01L29/78

Abstract: A semiconductor device, a field effect transistor, and a fin field effect transistor are provided. The semiconductor device may include a channel layer, a source/drain layer, and a gate electrode. The channel layer is provided on a substrate and extends in a direction perpendicular to a top surface of the substrate. The source/drain layer is disposed at a side of the channel layer and is electrically connected to the channel layer. The gate electrode is provided adjacent to at least one of surfaces of the channel layer. The channel layer includes a two-dimensional atomic layer made of a first material.

公开(公告)号：US20180197957A1

公开(公告)日：2018-07-12

申请号：US15911182

申请日：2018-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shigenobu MAEDA ,  Seunghan SEO ,  Yeohyun SUNG

IPC: H01L29/16 ,  H01L29/20 ,  H01L29/786 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165

Abstract: A semiconductor device, a field effect transistor, and a fin field effect transistor are provided. The semiconductor device may include a channel layer, a source/drain layer, and a gate electrode. The channel layer is provided on a substrate and extends in a direction perpendicular to a top surface of the substrate. The source/drain layer is disposed at a side of the channel layer and is electrically connected to the channel layer. The gate electrode is provided adjacent to at least one of surfaces of the channel layer. The channel layer includes a two-dimensional atomic layer made of a first material.

公开(公告)号：US20170047335A1

公开(公告)日：2017-02-16

申请号：US15334411

申请日：2016-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min CHOI ,  Shigenobu MAEDA ,  Jihoon YOON ,  SUNGMAN LIM

IPC: H01L27/112 ,  H01L23/525 ,  H01L23/522 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/11206 ,  H01L23/5226 ,  H01L23/5252 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/42372 ,  H01L29/785 ,  H01L29/7851

Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.

Abstract translation: 本发明构思提供半导体器件及其制造方法。 一个半导体器件包括衬底，设置在衬底上的器件隔离层，由器件隔离层限定并且具有高于器件隔离层的顶表面的顶表面的翅片型有源图案，设置在器件隔离层上的第一导电线 翅片型有源图案的边缘部分和与鳍式有源图案的边缘部分相邻的器件隔离层，以及设置在鳍式有源图案和第一导电线之间的绝缘薄层。 第一导线形成可以施加写入电压的反熔丝的栅电极。

公开(公告)号：US20160343575A1

公开(公告)日：2016-11-24

申请号：US15099945

申请日：2016-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu MAEDA ,  Jeong Ju Park ,  Eunsung Kim ,  Hyunwoo Kim ,  Shiyong Yi

IPC: H01L21/308 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method includes forming mask patterns spaced apart from each other by at least one opening on an etch target layer, filling the opening with a block copolymer material including first and second polymer blocks of different properties, and annealing the block copolymer material to form first patterns and second patterns, the first patterns in contact with facing sidewalls of adjacent ones of the mask patterns, respectively, and at least one of the second patterns between the first patterns. The first patterns include the first polymer blocks and the second patterns include the second polymer blocks.

Abstract translation: 一种方法包括形成通过蚀刻目标层上的至少一个开口彼此间隔开的掩模图案，用包含不同性质的第一和第二聚合物嵌段的嵌段共聚物材料填充该开口，并退火嵌段共聚物材料以形成第一图案 和第二图案，分别与相邻的掩模图案的面对的侧壁接触的第一图案以及第一图案之间的至少一个第二图案。 第一图案包括第一聚合物嵌段，第二图案包括第二聚合物嵌段。

公开(公告)号：US20150108602A1

公开(公告)日：2015-04-23

申请号：US14304750

申请日：2014-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min CHOI ,  Shigenobu MAEDA ,  Ji-Hoon YOON ,  Sung-Man LIM

IPC: H01L23/525 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a fuse area and a device area; a fuse structure in an insulating layer of the fuse area, and a wire structure in the insulating layer of the device area. The fuse structure includes a fuse via, a fuse line electrically connected to a top end of the fuse via pattern and extending in a direction. The wire structure includes a wire via, a wire line electrically connected to a top end of the wire via and extending in the first direction. A width in the first direction of the fuse via is smaller than a width in the first direction of the wire via.

Abstract translation: 半导体器件包括具有熔丝区域和器件区域的衬底; 保险丝区域的绝缘层中的熔丝结构，以及设备区域的绝缘层中的线结构。 熔丝结构包括熔丝通孔，熔丝线与熔丝通孔图案的顶端电连接并沿一个方向延伸。 导线结构包括导线通孔，电线连接到导线通孔的顶端并沿第一方向延伸的导线。 保险丝通孔的第一方向上的宽度小于电线通路的第一方向上的宽度。