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公开(公告)号：US10727078B2
公开(公告)日：2020-07-28
申请号：US15370290
申请日：2016-12-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeong Ju Park , Kyeongmi Lee , Seungchul Kwon , Eunsung Kim , Shiyong Yi
IPC: H01L21/027 , H01L21/311 , H01L21/308 , H01L21/033 , H01L21/3105 , H01L21/02
Abstract: A method of forming fine patterns includes forming a mask on an etching target, forming an anti-reflective layer on the mask, forming fixing patterns such that top surfaces of the anti-reflective layer and fixing patterns are exposed, forming a block copolymer layer including first and second polymer blocks, and phase-separating the block copolymer layer to form first patterns and second patterns on the anti-reflective layer and the fixing patterns. The first and second patterns include the first and second polymer blocks, respectively. The anti-reflective layer has a neutral, i.e., non-selective, interfacial energy with respect to the first and second polymer blocks. The fixing patterns have a higher interfacial energy with respect to the first polymer block than the second polymer block.
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公开(公告)号：US09954155B2
公开(公告)日：2018-04-24
申请号：US15280241
申请日：2016-09-29
Inventor： Seongjun Park , Hyeonjin Shin , Sungwng Kim , Eunsung Kim , Jaeyeol Hwang
CPC classification number: H01L35/16 , H01L21/02488 , H01L21/02502 , H01L35/10 , H01L35/18 , H01L35/34
Abstract: A thermoelectric structure that may be included in a thermoelectric device may include a thin-film structure that may include a plurality of thin-film layers. The thin-film structure may include Tellurium. The thin-film structure may be on a substrate. The substrate may include an oxide, and a buffer layer may be between the substrate and the thin-film structure. The thermoelectric structure may be manufactured via depositing material ablated from a target onto the substrate. Some material may react with the substrate to form the buffer layer, and thin film layers may be formed on the buffer layer. The thin film layers may be removed from the substrate and provided on a separate substrate. Removing the thin-film layers from the substrate may include removing the thin-film layers from the buffer layer.
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公开(公告)号：US20160343575A1
公开(公告)日：2016-11-24
申请号：US15099945
申请日：2016-04-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shigenobu MAEDA , Jeong Ju Park , Eunsung Kim , Hyunwoo Kim , Shiyong Yi
IPC: H01L21/308 , H01L21/3213 , H01L21/311
CPC classification number: H01L21/3086 , H01L21/0337 , H01L21/31144 , H01L21/32139
Abstract: A method includes forming mask patterns spaced apart from each other by at least one opening on an etch target layer, filling the opening with a block copolymer material including first and second polymer blocks of different properties, and annealing the block copolymer material to form first patterns and second patterns, the first patterns in contact with facing sidewalls of adjacent ones of the mask patterns, respectively, and at least one of the second patterns between the first patterns. The first patterns include the first polymer blocks and the second patterns include the second polymer blocks.
Abstract translation: 一种方法包括形成通过蚀刻目标层上的至少一个开口彼此间隔开的掩模图案，用包含不同性质的第一和第二聚合物嵌段的嵌段共聚物材料填充该开口，并退火嵌段共聚物材料以形成第一图案 和第二图案，分别与相邻的掩模图案的面对的侧壁接触的第一图案以及第一图案之间的至少一个第二图案。 第一图案包括第一聚合物嵌段，第二图案包括第二聚合物嵌段。
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Patent Agency Ranking
公开(公告)号：US20180212130A1
公开(公告)日：2018-07-26
申请号：US15933900
申请日：2018-03-23
Inventor： Seongjun PARK , Hyeonjin Shin , Sungwng Kim , Eunsung Kim , Jaeyeol Hwang Hwang
CPC classification number: H01L35/16 , H01L21/02488 , H01L21/02502 , H01L35/10 , H01L35/18 , H01L35/34
Abstract: A thermoelectric structure that may be included in a thermoelectric device may include a thin-film structure that may include a plurality of thin-film layers. The thin-film structure may include Tellurium. The thin-film structure may be on a substrate. The substrate may include an oxide, and a buffer layer may be between the substrate and the thin-film structure. The thermoelectric structure may be manufactured via depositing material ablated from a target onto the substrate. Some material may react with the substrate to form the buffer layer, and thin film layers may be formed on the buffer layer. The thin film layers may be removed from the substrate and provided on a separate substrate. Removing the thin-film layers from the substrate may include removing the thin-film layers from the buffer layer.
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公开(公告)号：US20160155743A1
公开(公告)日：2016-06-02
申请号：US14956049
申请日：2015-12-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eunsung Kim , Seungchul KWON , Kyoungseon KIM , Dong-Won KIM , Shiyong YI
IPC: H01L27/105 , H01L21/306 , H01L21/308 , H01L21/768
CPC classification number: H01L21/76816 , H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L27/10814 , H01L27/1157 , H01L27/11582
Abstract: A method for forming patterns of a semiconductor device includes forming a block copolymer layer on an underlying layer, the underlying layer including a first block copolymer having first and second polymer blocks; phase-separating the block copolymer layer to form first block portions including the first polymer block and a second block portion surrounding the first block portions and including the second polymer block; removing the first block portions to form first openings; forming block copolymer pillars to fill the first openings, the block copolymer pillars including a second block copolymer having third and fourth polymer blocks; phase-separating the block copolymer pillars to form third block portions including the third polymer block and fourth block portions including the fourth polymer block within the first openings; and removing the third block portions to form second openings.
Abstract translation: 用于形成半导体器件的图案的方法包括在下层上形成嵌段共聚物层，下层包括具有第一和第二聚合物嵌段的第一嵌段共聚物; 相分离所述嵌段共聚物层以形成包含所述第一聚合物嵌段的第一嵌段部分和围绕所述第一嵌段部分并包括所述第二聚合物嵌段的第二嵌段部分; 去除第一块部分以形成第一开口; 形成嵌段共聚物柱以填充第一开口，所述嵌段共聚物柱包括具有第三和第四聚合物嵌段的第二嵌段共聚物; 相分离嵌段共聚物柱以形成包含第三聚合物嵌段的第三嵌段部分和在第一开口内包含第四聚合物嵌段的第四嵌段部分; 并移除第三块部分以形成第二开口。
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公开(公告)号：US10854465B2
公开(公告)日：2020-12-01
申请号：US16023836
申请日：2018-06-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shigenobu Maeda , Jeong Ju Park , Eunsung Kim , Hyunwoo Kim , Shiyong Yi
IPC: H01L21/308 , H01L21/311 , H01L21/3213 , H01L21/033
Abstract: A method includes forming mask patterns spaced apart from each other by at least one opening on an etch target layer, filling the opening with a block copolymer material including first and second polymer blocks of different properties, and annealing the block copolymer material to form first patterns and second patterns, the first patterns in contact with facing sidewalls of adjacent ones of the mask patterns, respectively, and at least one of the second patterns between the first patterns. The first patterns include the first polymer blocks and the second patterns include the second polymer blocks.
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公开(公告)号：US10032638B2
公开(公告)日：2018-07-24
申请号：US15099945
申请日：2016-04-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shigenobu Maeda , Jeong Ju Park , Eunsung Kim , Hyunwoo Kim , Shiyong Yi
IPC: H01L21/311 , H01L21/308 , H01L21/3213 , H01L21/033
Abstract: A method includes forming mask patterns spaced apart from each other by at least one opening on an etch target layer, filling the opening with a block copolymer material including first and second polymer blocks of different properties, and annealing the block copolymer material to form first patterns and second patterns, the first patterns in contact with facing sidewalls of adjacent ones of the mask patterns, respectively, and at least one of the second patterns between the first patterns. The first patterns include the first polymer blocks and the second patterns include the second polymer blocks.
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公开(公告)号：US08652968B2
公开(公告)日：2014-02-18
申请号：US13719235
申请日：2012-12-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Han Geun Yu , Eunsung Kim , Chulho Shin
IPC: H01L21/311
CPC classification number: H01L21/02337 , H01L21/0337 , H01L21/0338 , H01L21/76816 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1675
Abstract: A method of fabricating a semiconductor device may include forming spacer line patterns on sidewalls of photoresist. A planarization etching process may be performed on a subsequently added planarization layer, after forming a mesh-shaped mask pattern from the spacer line patterns.
Abstract translation: 制造半导体器件的方法可以包括在光致抗蚀剂的侧壁上形成间隔线图案。 在从隔离线图案形成网状掩模图案之后，可以对随后添加的平坦化层执行平面化蚀刻工艺。
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