公开(公告)号：US09971697B2

公开(公告)日：2018-05-15

申请号：US15354354

申请日：2016-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chankyung Kim ,  Uksong Kang ,  Sanguhn Cha ,  Sungyong Seo ,  Youngjin Cho ,  Seongil O

IPC: G06F12/08 ,  G06F12/0871 ,  G11C11/4093 ,  G11C7/10 ,  G06F12/0802 ,  G06F12/0853

CPC classification number: G06F12/0871 ,  G06F11/1064 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0853 ,  G06F12/0868 ,  G06F12/0895 ,  G06F2212/1004 ,  G06F2212/1028 ,  G06F2212/205 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/313 ,  G06F2212/60 ,  G06F2212/601 ,  G06F2212/7203 ,  G11C5/04 ,  G11C7/1072 ,  G11C11/005 ,  G11C11/4093 ,  G11C16/0483

Abstract: A nonvolatile memory module includes at least one nonvolatile memory, at least one nonvolatile memory controller configured to control the nonvolatile memory, at least one dynamic random access memory (DRAM) used as a cache of the at least one nonvolatile memory, data buffers configured to store data exchanged between the at least one DRAM and an external device, and a memory module control device configured to control the nonvolatile memory controller, the at least one DRAM, and the data buffers. The at least one DRAM stores a tag corresponding to cache data and compares the stored tag with input tag information to determine whether to output the cache data.

公开(公告)号：US20160357462A1

公开(公告)日：2016-12-08

申请号：US15096877

申请日：2016-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee Hyun Nam ,  Jaegeun Park ,  Sungyong Seo ,  Youngkwang Yoo ,  Han-Ju Lee ,  Youngjin Cho

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0685

Abstract: Disclosed is a nonvolatile memory module. The nonvolatile memory module includes at least one nonvolatile memory, a random access memory (RAM) and a device controller. Responsive to receiving a write request comprising sub-data from a host, the device controller accumulates the sub-data in the RAM and programs the accumulated sub-data in the nonvolatile memory. A size of the sub-data is smaller than a size of a default transmission unit provided from the host.

Abstract translation: 公开了一种非易失性存储器模块。 非易失性存储器模块包括至少一个非易失性存储器，随机存取存储器（RAM）和器件控制器。 响应于从主机接收到包含子数据的写入请求，设备控制器将该子数据累加在RAM中，并将累积的子数据编程在非易失性存储器中。 子数据的大小小于从主机提供的默认传输单元的大小。