公开(公告)号：US11139806B2

公开(公告)日：2021-10-05

申请号：US16112921

申请日：2018-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-hyung Kim ,  Sung-jae Moon

IPC: G06F1/00 ,  H03K5/156 ,  G06F1/10

Abstract: A system on chip includes a clock generator configured to generate a clock signal, and output the clock signal to a component device external to the system on chip. The system on chip further includes a duty ratio determiner configured to determine a component duty ratio, in response to a response that is received from the component device according to the clock signal, and a duty ratio adjustor configured to adjust a current duty ratio of the clock signal to the component duty ratio, and output the clock signal of which the current duty ratio is adjusted, to the component device.

公开(公告)号：US20200168542A1

公开(公告)日：2020-05-28

申请号：US16774082

申请日：2020-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-hyung Kim ,  Jung-ho Do ,  Dae-young Moon ,  Sang-yeop Baeck ,  Jae-hyun Lim ,  Jae-seung Choi ,  Sang-shin Han

IPC: H01L23/528 ,  H01L29/45 ,  H01L29/417 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L23/522 ,  H01L27/118 ,  H01L27/088

Abstract: Provided is an integrated circuit which includes: a plurality of conductive lines extending in a first horizontal direction on a plane separate from a gate line, and including first and second conductive lines; a source/drain contact having a bottom surface connected to a source/drain region, and including a lower source/drain contact and an upper source/drain contact which are connected to each other in a vertical direction; and a gate contact having a bottom surface connected to the gate line, and extending in the vertical direction, in which the upper source/drain contact is placed below the first conductive line, and the gate contact is placed below the second conductive line. A top surface of the lower source/drain contact may be larger than a bottom surface of the upper source/drain contact.

公开(公告)号：US10580733B2

公开(公告)日：2020-03-03

申请号：US15909212

申请日：2018-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-hyung Kim ,  Jung-ho Do ,  Dae-young Moon ,  Sang-yeop Baeck ,  Jae-hyun Lim ,  Jae-seung Choi ,  Sang-shin Han

IPC: H01L23/528 ,  H01L27/088 ,  H01L27/118 ,  H01L23/522 ,  H01L27/092 ,  H01L27/02 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234

Abstract: Provided is an integrated circuit which includes: a plurality of conductive lines extending in a first horizontal direction on a plane separate from a gate line, and including first and second conductive lines; a source/drain contact having a bottom surface connected to a source/drain region, and including a lower source/drain contact and an upper source/drain contact which are connected to each other in a vertical direction; and a gate contact having a bottom surface connected to the gate line, and extending in the vertical direction, in which the upper source/drain contact is placed below the first conductive line, and the gate contact is placed below the second conductive line. A top surface of the lower source/drain contact may be larger than a bottom surface of the upper source/drain contact.

公开(公告)号：US10431272B2

公开(公告)日：2019-10-01

申请号：US15921771

申请日：2018-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-yeop Baeck ,  Siddharth Gupta ,  In-hak Lee ,  Jae-seung Choi ,  Tae-hyung Kim ,  Dae-young Moon ,  Dong-wook Seo

IPC: G11C8/08 ,  G11C5/14 ,  G11C11/419

Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.

公开(公告)号：US09946640B2

公开(公告)日：2018-04-17

申请号：US14656019

申请日：2015-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-sik Yun ,  Tae-hyung Kim

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F12/023 ,  G06F3/06 ,  G06F2212/1044

Abstract: A method of managing a memory of a device is provided. The method includes acquiring amount of memory use information of the device, estimating a memory use pattern, based on the amount of memory use information of the device, and acquiring an amount of memory of the device, based on the estimated memory use pattern.

公开(公告)号：US09567680B2

公开(公告)日：2017-02-14

申请号：US14143271

申请日：2013-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-gon Kim ,  Jeong-hee Lee ,  Seoung-jae Im ,  Tae-hyung Kim

IPC: C25B11/04 ,  C01B3/04 ,  C25B1/00

CPC classification number: C25B11/0478 ,  C01B3/042 ,  C25B1/00 ,  C25B1/003 ,  Y02E60/364 ,  Y02E60/368 ,  Y02P20/135 ,  Y10T428/12611 ,  Y10T428/12819

Abstract: A composite protective layer for a photoelectrode, the composite protective layer including a chemical protective layer; and a physical protective layer, wherein the chemical protective layer has corrosion rate of 0.1 Coulombs per square centimeter per 10 hours or less when evaluated at a water decomposition potential, and the physical protective layer has a moisture transmittance rate of 0.001 grams per square meter per day or less and has an electrical conductivity.

Abstract translation: 一种用于光电极的复合保护层，所述复合保护层包括化学保护层; 和物理保护层，其中当在水分解电位下进行评估时，化学保护层的腐蚀速率为每10平方厘米0.1平方厘米，并且物理保护层的水分透过率为0.001克/平方米/ 天或更少并且具有导电性。

公开(公告)号：US09290852B2

公开(公告)日：2016-03-22

申请号：US14076355

申请日：2013-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-hee Lee ,  Tae-gon Kim ,  Tae-hyung Kim ,  Seoung-jae Im

IPC: C25B11/00 ,  C25B11/04 ,  C25B1/00 ,  H01L31/0224

CPC classification number: C25B11/0478 ,  C25B1/003 ,  H01L31/0224 ,  Y02P20/135

Abstract: A light absorbing layer for a photoelectrode structure, the light absorbing layer including copper oxide, wherein metallic copper (Cu) is present at a grain boundary of the copper oxide. Also, a photoelectrode structure including the light absorbing layer, a photoelectrochemical cell including the photoelectrode structure, and a solar cell including the light absorbing layer.

Abstract translation: 一种光电极结构的光吸收层，其中包含氧化铜的光吸收层，其中金属铜（Cu）存在于氧化铜的晶界处。 此外，包括光吸收层的光电极结构，包括光电极结构的光电化学电池和包括光吸收层的太阳能电池。

公开(公告)号：US10564843B2

公开(公告)日：2020-02-18

申请号：US14912783

申请日：2014-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-hwan Choi ,  Young-jin Kim ,  Tae-soo Kim ,  Kang-tae Kim ,  Tae-hyung Kim

IPC: G06F3/048 ,  G06F3/0488 ,  G06F3/0481 ,  G06F3/0484

Abstract: A method of displaying for allowing a plurality of application windows to be easily controlled and a display device therefor are provided. A method of displaying a screen on a display device includes displaying a button on a touch screen; splitting the touch screen into a plurality of regions based on the position at which the button is displayed, receiving a touch input to move a displayed button, obtaining a slope value of a line connecting a start point of the touch input to an end point thereof, selecting a region corresponding to the slope value from among the plurality of regions split, and moving the button to a certain position included in a selected region.

公开(公告)号：US20180294219A1

公开(公告)日：2018-10-11

申请号：US15909212

申请日：2018-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-hyung Kim ,  Jung-ho Do ,  Dae-young Moon ,  Sang-yeop Baeck ,  Jae-hyun Lim ,  Jae-seung Choi ,  Sang-shin Han

IPC: H01L23/528 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L23/528 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/78 ,  H01L2027/11875

Abstract: Provided is an integrated circuit which includes: a plurality of conductive lines extending in a first horizontal direction on a plane separate from a gate line, and including first and second conductive lines; a source/drain contact having a bottom surface connected to a source/drain region, and including a lower source/drain contact and an upper source/drain contact which are connected to each other in a vertical direction; and a gate contact having a bottom surface connected to the gate line, and extending in the vertical direction, in which the upper source/drain contact is placed below the first conductive line, and the gate contact is placed below the second conductive line. A top surface of the lower source/drain contact may be larger than a bottom surface of the upper source/drain contact.

公开(公告)号：US10038127B2

公开(公告)日：2018-07-31

申请号：US15493883

申请日：2017-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-in Yang ,  Tae-hyung Kim ,  Si-hyuk Lee ,  Sang-yeob Song ,  Cheol-soo Sone ,  Hak-hwan Kim ,  Jin-hyun Lee

IPC: H01L33/00 ,  H01L33/62 ,  H01L33/20 ,  H01L33/32 ,  H01L33/38 ,  H01L33/40 ,  H01L33/44

CPC classification number: H01L33/62 ,  H01L33/0025 ,  H01L33/005 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/20 ,  H01L33/32 ,  H01L33/382 ,  H01L33/387 ,  H01L33/405 ,  H01L33/44 ,  H01L2924/0002 ,  H01L2933/0016 ,  H01L2933/0066 ,  H01L2924/00

Abstract: A semiconductor light-emitting device, and a method of manufacturing the same. The semiconductor light-emitting device includes a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked on a substrate, a first contact that passes through the substrate to be electrically connected to the first electrode layer, and a second contact that passes through the substrate, the first electrode layer, and the insulating layer to communicate with the second electrode layer. The first electrode layer is electrically connected to the first semiconductor layer by filling a contact hole that passes through the second electrode layer, the second semiconductor layer, and the active layer, and the insulating layer surrounds an inner circumferential surface of the contact hole to insulate the first electrode layer from the second electrode layer.