公开(公告)号：US10026652B2

公开(公告)日：2018-07-17

申请号：US15343157

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

Abstract: Multi-Vt horizontal nanosheet devices and a method of making the same. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet devices (hNS devices) on a top surface of a substrate, the plurality of hNS devices including a first hNS device and a second hNS device spaced apart from each other horizontally. Each of the hNS devices includes a first and a second horizontal nanosheets spaced apart vertically; and a gate stack between the first and second horizontal nanosheets, the gate stack including a work function metal (WFM) layer. A thickness of the first and second horizontal nanosheets of the first hNS device is different from a thickness of the first and second horizontal nanosheets of the second hNS device, and a thickness of the WFM layer of the first hNS device is different from a thickness of the WFM layer of the second hNS device.

公开(公告)号：US20180076199A1

公开(公告)日：2018-03-15

申请号：US15348916

申请日：2016-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Joon Goo Hong

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/321 ,  H01L29/04

Abstract: A complimentary metal-oxide-semiconductor (CMOS) circuit including: a substrate; and a plurality of field-effect transistors on the substrate. Each of the field-effect transistors includes: a plurality of contacts; a source connected to one of the contacts; a drain connected to another one of the contacts; a gate; and a spacer between the gate and the contacts. The spacer of one of the field-effect transistors has a larger airgap than the spacer of another one of the field-effect transistors.

公开(公告)号：US20180053859A1

公开(公告)日：2018-02-22

申请号：US15359480

申请日：2016-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Robert M. Wallace ,  Xiaoye Qin

IPC: H01L29/786 ,  H01L29/04 ,  H01L21/02

CPC classification number: H01L29/78681 ,  H01L21/02172 ,  H01L21/02293 ,  H01L29/04 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78696

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a substrate having a source region, a drain region, and a channel region between the source region and the drain region, the substrate having an epitaxial III-V material that includes three elements thereon, a source electrode over the source region, a drain electrode over the drain region, and a crystalline oxide layer including an oxide formed on the epitaxial III-V material in the channel region, the epitaxial III-V material including three elements.

公开(公告)号：US09698234B2

公开(公告)日：2017-07-04

申请号：US14666770

申请日：2015-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Mark S. Rodder ,  Wei-E Wang

IPC: H01L21/31 ,  H01L31/113 ,  H01L29/51 ,  H01L21/28 ,  H01L29/778

CPC classification number: H01L29/513 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/778

Abstract: Exemplary embodiments provide for fabricating a field effect transistor (FET) with an interface layer for a gate stack using an O3 post treatment. Aspects of the exemplary embodiments include: forming a semiconductor body upon a substrate; cleaning the surface of the semiconductor body; depositing a first dielectric layer on the semiconductor body; performing an O3 treatment to form a new interface layer that incorporates material from the substrate and material from the first dielectric layer; and performing gate stack processing, including deposition of a gate electrode.

公开(公告)号：US20230361194A1

公开(公告)日：2023-11-09

申请号：US18225028

申请日：2023-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wei-E Wang ,  Mark S. Rodder

IPC: H01L29/51 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/28 ,  H01L27/092

CPC classification number: H01L29/516 ,  H01L21/823857 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78696 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/0922

Abstract: A field-effect transistor (FET) device having a modulated threshold voltage (Vt) includes a source electrode, a drain electrode, a channel region extending between the source electrode and the drain electrode, and a gate stack on the channel region. The gate stack includes an ultrathin dielectric dipole layer configured to shift the modulated Vt in a first direction, a high-k (HK) insulating layer on the ultrathin dielectric dipole layer, and a gate metal layer on the HK insulating layer configured to shift the modulated Vt in a second direction.

公开(公告)号：US11158738B2

公开(公告)日：2021-10-26

申请号：US16548209

申请日：2019-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark Rodder ,  Vassilios Gerousis

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66

Abstract: A method of forming a stacked field effect transistor (FET) circuit is provided. The method includes providing a first wafer and a second wafer, forming a first dielectric layer on a surface of the first wafer, forming a second dielectric layer on a surface of the second wafer, and bonding the first wafer to the second wafer at the first dielectric layer and the second dielectric layer.

公开(公告)号：US20210183814A1

公开(公告)日：2021-06-17

申请号：US16861029

申请日：2020-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Vassilios Gerousis

IPC: H01L25/065 ,  H01L23/00

Abstract: A method of manufacturing a three-dimensional semiconductor device includes forming a bi-layer sacrificial stack on a top wafer and a bottom wafer each including a series of interconnects in a dielectric substrate. The bi-layer sacrificial stack includes a second sacrificial layer on a first sacrificial layer. The method also includes selectively etching the second sacrificial layers to form a first pattern of projections on the top wafer and a second pattern of projections on the bottom wafer. The first pattern of projections is configured to mesh with the second pattern of projections. The method also includes positioning the top wafer on the bottom wafer and releasing the top wafer such that engagement between the first pattern of projections and the second pattern of projections self-aligns the plurality of interconnects of the top wafer with the plurality of interconnects of the bottom wafer within a misalignment error.

公开(公告)号：US20200381414A1

公开(公告)日：2020-12-03

申请号：US16997732

申请日：2020-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Titash Rakshit ,  Borna J. Obradovic ,  Chris Bowen ,  Mark S. Rodder

IPC: H01L27/02 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/822 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/84 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06 ,  H01L27/092 ,  H01L29/04 ,  H01L29/16 ,  H01L29/47

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.

公开(公告)号：US10586738B2

公开(公告)日：2020-03-10

申请号：US15877931

申请日：2018-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/167 ,  H01L21/225 ,  H01L21/268 ,  H01L21/324 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

Abstract: A method for providing a semiconductor device and the device so formed are described. A doped semiconductor layer is deposited on a semiconductor underlayer. At least a portion of the semiconductor underlayer is exposed. A dopant for the doped semiconductor layer is selected from a p-type dopant and an n-type dopant. An ultraviolet-assisted low temperature (UVLT) anneal of the doped semiconductor layer is performed in an ambient. The ambient is selected from an oxidizing ambient and a nitriding ambient. The oxidizing ambient is used for the n-type dopant. The nitriding ambient is used for the p-type dopant. A sacrificial layer is formed by the doped semiconductor layer during the UVLT anneal. The dopant is driven into the portion of the semiconductor underlayer from the doped semiconductor layer by the UVLT anneal, thereby forming a doped semiconductor underlayer. The sacrificial layer is then removed.

公开(公告)号：US20190131182A1

公开(公告)日：2019-05-02

申请号：US15877931

申请日：2018-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/167 ,  H01L29/78 ,  H01L21/225 ,  H01L21/268 ,  H01L21/324 ,  H01L21/02

Abstract: A method for providing a semiconductor device and the device so formed are described. A doped semiconductor layer is deposited on a semiconductor underlayer. At least a portion of the semiconductor underlayer is exposed. A dopant for the doped semiconductor layer is selected from a p-type dopant and an n-type dopant. An ultraviolet-assisted low temperature (UVLT) anneal of the doped semiconductor layer is performed in an ambient. The ambient is selected from an oxidizing ambient and a nitriding ambient. The oxidizing ambient is used for the n-type dopant. The nitriding ambient is used for the p-type dopant. A sacrificial layer is formed by the doped semiconductor layer during the UVLT anneal. The dopant is driven into the portion of the semiconductor underlayer from the doped semiconductor layer by the UVLT anneal, thereby forming a doped semiconductor underlayer. The sacrificial layer is then removed.