公开(公告)号：US10852969B2

公开(公告)日：2020-12-01

申请号：US16363034

申请日：2019-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjun Yu ,  Insu Choi ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin

IPC: G06F3/06 ,  G06F12/0802

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

公开(公告)号：US11887692B2

公开(公告)日：2024-01-30

申请号：US17535861

申请日：2021-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonjae Shin ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Deokho Seo ,  Insu Choi

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18

CPC classification number: G11C7/222 ,  G11C7/1009 ,  G11C7/109 ,  G11C7/1063 ,  G11C8/18

Abstract: An operation method of a memory device, having a plurality of memory cells, includes receiving a partial write command, which includes a partial write enable signal (PWE) and a plurality of mask signals, during a command/address input interval. A data strobe signal is received through a data strobe line after receiving the partial write command Data is received through a plurality of data lines in synchronization with the data strobe signal during a data input interval. A part of the data is stored in the plurality of memory cells based on the plurality of mask signals, in response to the partial write enable signal, during a data write interval.

公开(公告)号：US11670355B2

公开(公告)日：2023-06-06

申请号：US17406511

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/40618

Abstract: Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

公开(公告)号：US11321177B2

公开(公告)日：2022-05-03

申请号：US17108331

申请日：2020-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Deokho Seo ,  Wonjae Shin ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G06F11/10 ,  G11C11/4091 ,  G11C11/408

Abstract: A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.

公开(公告)号：US20200174882A1

公开(公告)日：2020-06-04

申请号：US16412468

申请日：2019-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/00 ,  G11C11/406

Abstract: A memory system includes a memory device having a plurality of volatile memory modules therein, and a memory controller, which is electrically coupled to the plurality of volatile memory modules. The memory controller is configured to correct an error in a first of the plurality of volatile memory modules in response to generation of an alert signal by the first of the plurality of volatile memory modules, concurrently with an operation to refresh at least a portion of a second of the plurality of volatile memory modules upon the generation of the alert signal.

公开(公告)号：US20190310905A1

公开(公告)日：2019-10-10

申请号：US16164103

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonjae Shin ,  Tae-Kyeong KO ,  Dae-Jeong KIM ,  Sung-Joon KIM ,  Wooseop KIM ,  Chanik PARK ,  Yongjun YU ,  lnsu CHOI ,  Hui-Chung BYUN ,  JongYoung LEE

IPC: G06F11/07

Abstract: A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.

公开(公告)号：US11210208B2

公开(公告)日：2021-12-28

申请号：US16162821

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong Kim ,  Jiseok Kang ,  Tae-Kyeong Ko ,  Sung-Joon Kim ,  Wooseop Kim ,  Chanik Park ,  Wonjae Shin ,  Yongjun Yu ,  Insu Choi

IPC: G06F12/02 ,  G11C11/56 ,  G06F3/06 ,  G06F13/16

Abstract: A memory system includes a nonvolatile memory module and a first controller configured to control the nonvolatile memory module. The nonvolatile memory module includes a volatile memory device, a nonvolatile memory device, and a second controller configured to control the volatile memory device and the nonvolatile memory device. The first controller may be configured to transmit a read request to the second controller. When, during a read operation according to the read request, normal data is not received from the nonvolatile memory device, the first controller may perform one or more retransmits of the read request to the second controller without a limitation on a number of times that the first controller performs the one or more retransmits of the read request.

公开(公告)号：US10922170B2

公开(公告)日：2021-02-16

申请号：US16412468

申请日：2019-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G11C29/00 ,  G06F11/10 ,  G11C11/406 ,  G11C11/00 ,  G11C29/52

Abstract: A memory system includes a memory device having a plurality of volatile memory modules therein, and a memory controller, which is electrically coupled to the plurality of volatile memory modules. The memory controller is configured to correct an error in a first of the plurality of volatile memory modules in response to generation of an alert signal by the first of the plurality of volatile memory modules, concurrently with an operation to refresh at least a portion of a second of the plurality of volatile memory modules upon the generation of the alert signal.

公开(公告)号：US20210042046A1

公开(公告)日：2021-02-11

申请号：US17082448

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjun Yu ,  Insu Choi ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin

IPC: G06F3/06 ,  G06F12/0802

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

公开(公告)号：US10884655B2

公开(公告)日：2021-01-05

申请号：US16386645

申请日：2019-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Kim ,  Tae-Kyeong Ko ,  Dae-Jeong Kim ,  Do-Han Kim ,  Sung-Joon Kim ,  Wonjae Shin ,  Kwanghee Lee ,  Changmin Lee ,  Insu Choi

IPC: G06F3/06 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/02

Abstract: A storage module includes a dynamic random access memory (DRAM) device, a nonvolatile memory device, and a high-speed buffer memory. An method of operating the storage module includes copying target data stored in the nonvolatile memory device to the high-speed buffer memory in response to an external device entering a page fault mode, receiving a first refresh command from the external device, and, in response to the first refresh command, performing a first refresh operation associated with the DRAM device and moving the target data copied to the high-speed buffer memory to the DRAM device during a first refresh reference time.