公开(公告)号：US11239334B2

公开(公告)日：2022-02-01

申请号：US16811605

申请日：2020-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Tae Hwang ,  Wandon Kim ,  Geunwoo Kim

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/532 ,  H01L29/08 ,  H01L21/285 ,  H01L29/45 ,  H01L29/78

Abstract: A semiconductor device including a lower contact pattern including a first metal, an upper contact pattern including a second metal, a first resistivity of first metal being greater than a second resistivity of the second metal, and a metal barrier layer between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first and second metals may be provided. A lower width of the upper contact pattern may be less than an upper width of the lower contact pattern.

公开(公告)号：US20240250088A1

公开(公告)日：2024-07-25

申请号：US18600403

申请日：2024-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon Tae Hwang ,  Sunjung Lee ,  Heonbok Lee ,  Geunwoo Kim ,  Wandon Kim

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871

Abstract: A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

公开(公告)号：US12046556B2

公开(公告)日：2024-07-23

申请号：US17475141

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Wan Don Kim ,  Hyun Bae Lee ,  Yoon Tae Hwang

IPC: H01L23/528 ,  H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: A FINFET includes a substrate having a semiconductor fin extending upward from a first surface thereof, and first and second power rails on first and second opposing sides of the semiconductor fin, respectively. A base of the semiconductor fin may be recessed within a trench within the surface of the substrate, and the first and second power rails may at least partially fill the trench. A through-substrate via may be provided, which extends from adjacent a second surface of the substrate to at least one of the first and second power rails. A source/drain contact is also provided, which is electrically connected to a source/drain region of the FINFET and at least one of the first and second power rails.

公开(公告)号：US11955487B2

公开(公告)日：2024-04-09

申请号：US17886878

申请日：2022-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon Tae Hwang ,  Sunjung Lee ,  Heonbok Lee ,  Geunwoo Kim ,  Wandon Kim

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871

Abstract: A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

公开(公告)号：US10438800B2

公开(公告)日：2019-10-08

申请号：US15825135

申请日：2017-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Tae Hwang ,  Moon Kyun Song ,  Nam Gyu Cho ,  Kyu Min Lee ,  Soo Jung Choi ,  Yong Ho Ha ,  Sang Jin Hyun

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/786 ,  H01L29/78

Abstract: Semiconductor devices and methods for fabricating the same are provided. A semiconductor device may include a substrate including first and second regions, a first interface film disposed on the substrate in the first region, a second interface film disposed on the substrate in the second region, a dielectric film disposed on the first and second interface films, a first metal film disposed on the dielectric film in the first region, and a second metal film disposed on the dielectric film in the second region. The first and second interface films may comprise an oxide of the substrate, the first and second metal films may comprise different materials, and the first and second interface films may have different thicknesses. Channels may be provided in the first and second regions, and the channels may be fin-shaped or wire-shaped. The metal films may have different oxygen content.

公开(公告)号：US20180226300A1

公开(公告)日：2018-08-09

申请号：US15858403

申请日：2017-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Kyun Song ,  Yoon Tae Hwang ,  Kyu Min Lee ,  Soo Jung Choi

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823821 ,  H01L27/0605 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7856

Abstract: Semiconductor devices may include a substrate including first to third regions, with first to third interfacial layers in the first to third regions, respectively, first to third high-k dielectric films on the first to third interfacial layers, respectively, first to third work function adjustment films on the first to third high-k dielectric films, respectively, and first to third filling films on the first to third work function adjustment films, respectively. Concentrations of a dipole forming element in the first to third high-k dielectric films may be first to third concentrations. The first concentration may be greater than the second concentration, and the second concentration may be greater than the third concentration. Thicknesses of the first to third work function adjustment films may be first to third thicknesses. The first thickness may be less than the second thickness, and the second thickness may be less than the third thickness.

公开(公告)号：US20180151376A1

公开(公告)日：2018-05-31

申请号：US15797340

申请日：2017-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung Choi ,  Moonkyun Song ,  Yoon Tae Hwang ,  Kyumin Lee ,  Sangjin Hyun

IPC: H01L21/28 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/324 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L21/3105

CPC classification number: H01L21/28185 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/82345 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device includes forming first and second gate dielectric layers on first and second regions of a semiconductor substrate, respectively, forming a first metal-containing layer on the first and second gate dielectric layers, performing a first annealing process with respect to the first metal-containing layer, removing the first metal-containing layer from the first region, forming a second metal-containing layer on an entire surface of the semiconductor substrate, performing a second annealing process with respect to the second metal-containing layer, forming a gate electrode layer on the second metal-containing layer, and partially removing the gate electrode layer, the second metal-containing layer, the first metal-containing layer, the first gate dielectric layer, and the second gate dielectric layer to form first and second gate patterns on the first and second regions, respectively.