公开(公告)号：US10929223B2

公开(公告)日：2021-02-23

申请号：US16405427

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu Oh ,  Young-Jin Cho ,  Young-Geun Lee

IPC: G06F11/10 ,  G11C29/52 ,  G11C13/00 ,  G11C11/16

Abstract: A memory controller is provided. The memory controller includes an error correction code (ECC) circuit configured to correct an error of a read codeword provided from a memory device, the ECC circuit including: a codeword combination generator configured to receive a first read codeword including a plurality of first read codeword bit values that are read from a first region of the memory device, generate a change codeword by changing values of one or more of the plurality of first read codeword bit values, and provide a codeword combination including the change codeword; and an ECC decoder including a plurality of ECC engines, wherein the ECC decoder is configured to perform ECC decoding in parallel on a plurality of codewords included in the codeword combination.

公开(公告)号：US09799411B2

公开(公告)日：2017-10-24

申请号：US14705745

申请日：2015-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Cheol Hong ,  Young-Jin Cho ,  Dong-Gi Lee ,  Hee-Chang Cho

IPC: G11C17/00 ,  G11C29/52 ,  G06F13/16 ,  G11C5/04

CPC classification number: G11C29/52 ,  G06F13/1684 ,  G11C5/04

Abstract: A memory module set includes a main integrated circuit (IC) for transmitting and receiving an electrical signal, a first group of memory modules including at least one memory module having a first pin unit connected to the main IC, and a second group of memory modules including at least one memory module having a second pin unit connected to the main IC. The groups of memory modules and the main IC are arrayed in a first direction on a substrate, and the second group of memory modules is offset with respect to the first group of memory modules in a second direction that is perpendicular to the first direction so as to have a position relative to the main IC in the second direction that is different from that of the first group of memory modules.

公开(公告)号：US20140006646A1

公开(公告)日：2014-01-02

申请号：US13791153

申请日：2013-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Jin Cho ,  Ho-Ha Kim

IPC: G06F13/12

CPC classification number: G06F13/126 ,  G06F3/0679 ,  G06F13/385

Abstract: A semiconductor device includes a delay unit determining a delay value. A FIS (Frame Information Structure) receiver is connected to a transfer channel and receives a first H2D (Host to Device) FIS including first command information. A FIS generator is connected to a receiving channel and successively outputs a first DMA (Direct Memory Access) setup FIS, a first data FIS, and a first SDB (Set Device Bits) FIS after outputting a first D2H (Device to Host) FIS in response to the first H2D FIS, and to insert a delay period as large as the delay value next to the first data FIS or the first SDB FIS.

Abstract translation: 半导体器件包括确定延迟值的延迟单元。 FIS（帧信息结构）接收器连接到传送信道并接收包括第一命令信息的第一H2D（主机到设备）FIS。 FIS发生器连接到接收通道，并在输出第一个D2H（设备到主机）FIS之后，依次输出第一个DMA（直接存储器访问）设置FIS，第一个数据FIS和第一个SDB（设置设备位）FIS 响应于第一个H2D FIS，并且插入与第一数据FIS或第一SDB FIS旁边的延迟值一样大的延迟周期。

公开(公告)号：US11625063B2

公开(公告)日：2023-04-11

申请号：US17338320

申请日：2021-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Jin Cho ,  Jae-Geun Park ,  Young-Kwang Yoo ,  Soon-Suk Hwang

IPC: G06F1/10 ,  G06F1/04 ,  G06F5/06

Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.

公开(公告)号：US11054855B2

公开(公告)日：2021-07-06

申请号：US16149987

申请日：2018-10-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Jin Cho ,  Jae-Geun Park ,  Young-Kwang Yoo ,  Soon-Suk Hwang

IPC: G06F1/10 ,  G06F1/04 ,  G06F5/06

Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.

公开(公告)号：US09768106B2

公开(公告)日：2017-09-19

申请号：US14993044

申请日：2016-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Jin Cho ,  Jong-Min Jung ,  Yun-Ji Hur ,  Sung-Sik Park ,  Keun-Bong Lee

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  G02F1/1345 ,  H01L23/14

CPC classification number: H01L23/4985 ,  G02F1/13452 ,  H01L23/145 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/00 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip-on-film (COF) package includes a base film, a semiconductor chip mounted on a chip mounting region of a top surface of the base film, a plurality of top inner output conductive patterns, a plurality of bottom inner output conductive patterns and a plurality of landing vias. The top inner output conductive patterns are formed on the top surface of the base film and respectively connected to chip inner output pads formed on a bottom surface of the semiconductor chip. The bottom inner output conductive patterns are formed on a bottom surface of the base film. The landing vias are formed to vertically penetrate the base film and to respectively connect the top inner output conductive patterns and the bottom inner output conductive patterns. The landing vias are arranged within the chip mounting region to form a two-dimensional shape.