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    Photographing lens
    12.
    再颁专利
    Photographing lens 有权

    公开(公告)号：USRE46507E1

    公开(公告)日：2017-08-08

    申请号：US14753849

    申请日：2015-06-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young-Woo Park

    IPC: G02B13/22 ,  G02B13/18 ,  G02B9/34 ,  G02B15/173 ,  G02B13/16 ,  G02B13/00 ,  G02B27/28

    CPC classification number: G02B9/34 ,  G02B13/004 ,  G02B13/16 ,  G02B13/18 ,  G02B13/22 ,  G02B15/173 ,  G02B27/286

    Abstract: The present invention is directed to a photographing lens containing, in order from an object side: a first lens having a positive refractive power and a convex surface facing the object side; a second lens having a negative refractive power; a third lens having a positive refractive power; and a fourth lens having a negative refractive power and at least one aspheric surface, the photographing lens satisfying the following conditional expressions: L T f ≤ 1.2 0.5 ≤ f 3 f ≤ 1.0 where LT denotes the distance on the optical axis between the object side of the first lens and the image side of the fourth lens; f denotes the total focal length of the photographing lens; and f3 denotes the focal length of the third lens.

    Semiconductor devices
    13.
    发明授权
    Semiconductor devices 有权
    半导体器件

    公开(公告)号：US09508738B2

    公开(公告)日：2016-11-29

    申请号：US14591929

    申请日：2015-01-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Duk Lee ,  Young-Woo Park

    IPC: H01L29/66 ,  H01L27/115

    CPC classification number: H01L21/02636 ,  H01L21/28282 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582

    Abstract: A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other.

    Abstract translation: 半导体器件包括下绝缘层，在下绝缘层上彼此分离的多个基底层图案，在基底层图案之间的分离层图案，在垂直方向上延伸的多个通道相对于 基底层图案和围绕通道的外侧壁的多条栅极线在垂直方向上堆叠并彼此间隔开。

    NAND flash memory device
    14.
    发明授权
    NAND flash memory device 有权
    NAND闪存设备

    公开(公告)号：US08878332B2

    公开(公告)日：2014-11-04

    申请号：US14248517

    申请日：2014-04-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-Hoon Na ,  Young-Woo Park ,  Dong-Hwa Kwak ,  Tae-Yong Kim ,  Jee-Hoon Han ,  Jang-Hyun You ,  Dong-Sik Lee ,  Su-Jin Park

    IPC: H01L21/70 ,  H01L21/76 ,  H01L27/02 ,  H01L27/11

    CPC classification number: H01L27/0207 ,  H01L21/28273 ,  H01L27/11 ,  H01L27/11519 ,  H01L27/11524

    Abstract: A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.

    Abstract translation: 一种制造非易失性存储器件的方法包括提供具有由多个沟槽限定的有源区的衬底，在具有多个沟槽的衬底上形成第一隔离层，在第一隔离层上形成牺牲层以填充沟槽， 所述牺牲层包括填充所述沟槽的下部的第一区域和除所述下部以外的第二区域填充部分，去除所述牺牲层的所述第二区域，在所述第一隔离层上形成第二隔离层和在所述第一隔离层的所述第一区域 牺牲层，通过去除牺牲层的第一区域在沟槽中形成气隙，以及在保持气隙的同时去除第一隔离层的一部分和第二隔离层的一部分。

    METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES INCLUDING VOIDS BETWEEN ACTIVE REGIONS AND RELATED DEVICES
    15.
    发明申请
    METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES INCLUDING VOIDS BETWEEN ACTIVE REGIONS AND RELATED DEVICES 有权
    制造非活性存储器件的方法，包括有源区域和相关器件之间的失调

    公开(公告)号：US20140248755A1

    公开(公告)日：2014-09-04

    申请号：US14279786

    申请日：2014-05-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong-Sik Lee ,  Jang-Hyun You ,  Jee-Hoon Han ,  Young-Woo Park ,  Sung-Hoi Hur ,  Sang-Ick Joo

    IPC: H01L21/762

    CPC classification number: H01L21/76224 ,  H01L21/76229 ,  H01L21/764

    Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.

    Abstract translation: 制造非易失性存储器件的方法包括在衬底中形成限定器件隔离区域的衬底中的沟槽，并且其间的有源区域。 沟槽和其间的有源区延伸到衬底的第一和第二器件区域。 牺牲层形成在第一器件区域中的有源区之间的沟槽中，并且形成绝缘层以基本上填充第二器件区域中的有源区之间的沟槽。 选择性地去除第一器件区域中的沟槽中的牺牲层的至少一部分以限定沿着第一器件区域中的有源区之间的沟槽延伸的间隙区域，同时基本上将绝缘层保持在有源区域之间的沟槽中 在第二设备区域中。 还讨论了相关的方法和设备。

    Methods of manufacturing vertical memory devices
    17.
    发明授权
    Methods of manufacturing vertical memory devices 有权

    公开(公告)号：US10453859B2

    公开(公告)日：2019-10-22

    申请号：US16117036

    申请日：2018-08-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kohji Kanamori ,  Shin-Hwan Kang ,  Young-Woo Park ,  Jung-Hoon Park

    IPC: H01L27/11582 ,  H01L29/423 ,  H01L29/788 ,  H01L49/02

    Abstract: A vertical memory device includes insulating interlayer patterns, of gate electrodes, a channel, and a charge storage pattern structure. The insulating interlayer patterns are spaced in a first direction. The gate electrodes between are neighboring insulating interlayer patterns, respectively. The channel extends through the insulating interlayer patterns and the gate electrodes in the first direction. The charge storage pattern structure includes a tunnel insulation pattern, a charge trapping pattern structure, and a blocking pattern sequentially stacked between the channel and each of the gate electrodes in a second direction. The charge trapping pattern structure includes charge trapping patterns spaced in the first direction. The charge trapping patterns are adjacent to sidewalls of first gate electrodes, respectively. A first charge trapping pattern extends in the first direction along a sidewall of a first insulating interlayer pattern.

    Non-volatile memory device
    18.
    发明授权
    Non-volatile memory device 有权

    公开(公告)号：US10199389B2

    公开(公告)日：2019-02-05

    申请号：US15485334

    申请日：2017-04-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-Won Kim ,  Chang-Seok Kang ,  Young-Woo Park ,  Jae-Goo Lee ,  Jae-Duk Lee

    IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/528

    Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

    Vertical memory devices and methods of manufacturing the same
    19.
    发明授权
    Vertical memory devices and methods of manufacturing the same 有权

    公开(公告)号：US10068917B2

    公开(公告)日：2018-09-04

    申请号：US15414890

    申请日：2017-01-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kohji Kanamori ,  Shin-Hwan Kang ,  Young-Woo Park ,  Jung-Hoon Park

    IPC: H01L27/11582 ,  H01L29/423 ,  H01L29/788 ,  H01L49/02

    Abstract: A vertical memory device includes insulating interlayer patterns, of gate electrodes, a channel, and a charge storage pattern structure. The insulating interlayer patterns are spaced in a first direction. The gate electrodes between are neighboring insulating interlayer patterns, respectively. The channel extends through the insulating interlayer patterns and the gate electrodes in the first direction. The charge storage pattern structure includes a tunnel insulation pattern, a charge trapping pattern structure, and a blocking pattern sequentially stacked between the channel and each of the gate electrodes in a second direction. The charge trapping pattern structure includes charge trapping patterns spaced in the first direction. The charge trapping patterns are adjacent to sidewalls of first gate electrodes, respectively. A first charge trapping pattern extends in the first direction along a sidewall of a first insulating interlayer pattern.

    Non-volatile memory device
    20.
    发明授权
    Non-volatile memory device 有权

    公开(公告)号：US09646984B2

    公开(公告)日：2017-05-09

    申请号：US15264902

    申请日：2016-09-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-Won Kim ,  Chang-Seok Kang ,  Young-Woo Park ,  Jae-Goo Lee ,  Jae-Duk Lee

    IPC: H01L27/115 ,  H01L27/1157 ,  H01L27/11582

    CPC classification number: H01L27/1157 ,  H01L27/11582

    Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

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