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公开(公告)号：US20220294476A1
公开(公告)日：2022-09-15
申请号：US17689462
申请日：2022-03-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Changkyu SEOL , Jiyoup KIM , Hyejeong SO , Myoungbo KWAK , Pilsang YOON , Sucheol LEE , Youngdon CHOI , Junghwan CHOI
Abstract: Encoding and decoding apparatuses and methods for implementing multi-mode coding are provided. The apparatus includes a transmitter and a receiver connected to a data bus. When data bursts are converted by the transmitter into codewords each including a plurality of symbols and/or a codeword received by the receiver is recovered as data bursts, maximum transition avoidance (MTA) codeword mappings in which no maximum transition (MT) event occurs between the plurality of symbols and minimum DC current (MDC) codeword mappings related to minimum power consumption of the plurality of symbols are used.
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12.发明申请公开(公告)号：US20220190936A1
公开(公告)日：2022-06-16
申请号：US17366329
申请日：2021-07-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyungmin JIN , Younghoon SON , Hyunyoon CHO , Youngdon CHOI , Junghwan CHOI
Abstract: A translation device, a test system, and a memory system are provided. The translation device includes plural first input/output (I/O) circuits that respectively transmit and receive first signals through plural pins based on a pulse amplitude modulation (PAM)-M mode, a second I/O circuit that transmits and receives a second signal through one or more pins based on a PAM-N mode, and a translation circuit that translates the first signals into the second signal and translates the second signal into the first signals. M and N are different integers of 2 or more.
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公开(公告)号：US20220068332A1
公开(公告)日：2022-03-03
申请号：US17344610
申请日：2021-06-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sucheol LEE , Jaewoo PARK , Younghoon SON , Youngdon CHOI , Junghwan CHOI
IPC: G11C7/22 , G11C7/10 , H03K19/017 , H03K19/1776 , H03K19/17736
Abstract: A memory device includes a memory cell array and a data input and output circuit configured to output a data signal (DQ signal) including data read from the memory cell array and a data strobe signal (DQS signal) including a toggle pattern associated with an operating condition of the memory device based on n-level pulse amplitude modulation (PAMn), wherein n is an integer greater than or equal to 4.
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公开(公告)号：US20240221795A1
公开(公告)日：2024-07-04
申请号：US18231935
申请日：2023-08-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngwoo PARK , Tongsung KIM , Youngmin KIM , Seungjin PARK , Seunghoon LEE , Chaekang LIM , Youngchul CHO , Youngdon CHOI , Junghwan CHOI
CPC classification number: G11C7/1048 , H03F3/45475 , H03K5/24 , H03M1/0607 , H03F2200/375 , H03F2203/45044 , H03F2203/45212
Abstract: A data converter including an autozeroing circuit including a plurality of gain circuits having a first amplification circuit and a first capacitor connected to the first amplification circuit, the first amplification circuit performing a switch feedthrough offset cancellation operation of storing an offset voltage of the autozeroing circuit in the capacitor through a switch, a comparator circuit including a first input terminal and a second input terminal, the comparator circuit comparing a first input terminal voltage level of the first input terminal with a second input terminal voltage level of the second input terminal, a first switch unit connected between the autozeroing circuit and the comparator circuit, the first switch disconnecting the autozeroing circuit from the comparator circuit during the switch feedthrough offset cancellation operation of the autozeroing circuit, and a second switch unit connected between a first input signal line and a second input signal line.
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公开(公告)号：US20230170003A1
公开(公告)日：2023-06-01
申请号：US18046030
申请日：2022-10-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Baek Jin LIM , Youngchul CHO , Seungjin PARK , Doobock LEE , Youngdon CHOI , Junghwan CHOI
IPC: G11C7/10 , G11C8/10 , H03K19/0175 , G11C7/04
CPC classification number: G11C7/1063 , G11C8/10 , H03K19/017545 , G11C7/1036 , G11C7/04 , G11C2207/2254
Abstract: There is provided a semiconductor device, which includes a calibration code generator circuit configured to generate a calibration code according to changes in external conditions, a first driver circuit configured to output a data signal with an impedance value controlled by the calibration code, an emphasis control circuit configured to generate an emphasis data signal using the data signal, and to change the calibration code according to an operating frequency to generate an emphasis code; and a second driver circuit configured to output the emphasis data signal with an impedance value controlled by the emphasis code.
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Patent Agency Ranking
16.发明申请公开(公告)号：US20230116188A1
公开(公告)日：2023-04-13
申请号：US17943448
申请日：2022-09-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyunsub RIE , Eunseok SHIN , Youngdon CHOI , Changsoo YOON , Hyunyoon CHO , Junghwan CHOI
IPC: G11C11/4096 , H03M1/12
Abstract: A receiver receiving a multi-level signal includes a sample and hold circuit, first and second analog-to-digital converting circuits, and a digital-to-analog converting circuit. The sample and hold circuit generates a sample data signal by sampling and holding an input data signal. The first analog-to-digital converting circuit generates a first bit of output data based on the input data signal and a first selection reference voltage among a plurality of reference voltages. The digital-to-analog converting circuit selects at least one additional selection reference voltage from among the plurality of reference voltages based on the first bit of the output data. The second analog-to-digital converting circuit generates at least one additional bit of the output data based on the sample data signal and the at least one additional selection reference voltage.
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公开(公告)号：US20220254391A1
公开(公告)日：2022-08-11
申请号：US17732220
申请日：2022-04-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunyoon CHO , Sukhee CHO , Younghoon SON , Youngdon CHOI , Junghwan CHOI
Abstract: A method of operating a memory device includes receiving a training request for a data channel, detecting at least one mode parameter according to the training request, transmitting the detected mode parameter to an external device, setting at least one of an NRZ mode and a PAM4 mode to a transmission signaling mode based on mode register set setting information from the external device, and performing communications with the external device according to the set transmission signaling mode.
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公开(公告)号：US20220209729A1
公开(公告)日：2022-06-30
申请号：US17536064
申请日：2021-11-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Baekjin LIM , Youngchul CHO , Seungjin PARK , Youngdon CHOI , Junghwan CHOI
IPC: H03F3/45
Abstract: An amplifier circuit comprises a first unit circuit and a second unit circuit. The first unit circuit may include a first current mirror circuit that includes a first active inductor including a P-channel transistor, and a first input circuit configured to generate a first differential current and a second differential current based on a pair of differential input signals. The second unit circuit may include a second current mirror circuit that includes a second active inductor including a P-channel transistor, and a second input circuit configured to generate a third differential current and a fourth differential current based on the pair of differential input signals.
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公开(公告)号：US20220121582A1
公开(公告)日：2022-04-21
申请号：US17326513
申请日：2021-05-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyungmin JIN , Jindo BYUN , Younghoon SON , Youngdon CHOI , Junghwan CHOI
Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.
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公开(公告)号：US20220059144A1
公开(公告)日：2022-02-24
申请号：US17229055
申请日：2021-04-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunyoon CHO , Sukhee CHO , Younghoon SON , Youngdon CHOI , Junghwan CHOI
Abstract: A method of operating a memory device includes receiving a training request for a data channel, detecting at least one mode parameter according to the training request, transmitting the detected mode parameter to an external device, setting at least one of an NRZ mode and a PAM4 mode to a transmission signaling mode based on mode register set setting information from the external device, and performing communications with the external device according to the set transmission signaling mode.
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