公开(公告)号：US20220093796A1

公开(公告)日：2022-03-24

申请号：US17542969

申请日：2021-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyujin KIM ,  Hui-Jung KIM ,  Junsoo KIM ,  Sangho LEE ,  Jae-Hwan CHO ,  Yoosang HWANG

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/311 ,  H01L27/108 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234

Abstract: A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.

公开(公告)号：US20200381436A1

公开(公告)日：2020-12-03

申请号：US16744871

申请日：2020-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungjun NOH ,  Junsoo KIM ,  Dongsoo WOO ,  Namho JEON

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/51 ,  H01L21/265 ,  H01L21/3115

Abstract: An integrated circuit device includes: a substrate including active regions; a device isolation film defining the active regions; a word line arranged over the active regions and the device isolation film and extending in a first horizontal direction; and a gate dielectric film arranged between the substrate and the word line and between the device isolation film and the word line, in which, in a second horizontal direction orthogonal to the first horizontal direction, a width of a second portion of the word line over the device isolation film is greater than a width of a first portion of the word line over the active regions. To manufacture the integrated circuit device, an impurity region is formed in the substrate and the device isolation film by implanting dopant ions into the substrate and the device isolation film, and a thickness of a portion of the impurity region is reduced.

公开(公告)号：US20190164985A1

公开(公告)日：2019-05-30

申请号：US16027887

申请日：2018-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Junsoo KIM ,  Hui-Jung KIM ,  Bong-Soo KIM ,  Satoru YAMADA ,  Kyupil LEE ,  Sunghee HAN ,  HyeongSun HONG ,  Yoosang HWANG

IPC: H01L27/11556 ,  H01L23/532 ,  H01L27/11524 ,  H01L49/02 ,  G11C8/14 ,  G11C7/18

Abstract: A semiconductor memory device comprises a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also comprises a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer comprises semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

公开(公告)号：US20250098269A1

公开(公告)日：2025-03-20

申请号：US18762812

申请日：2024-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun CHOI ,  Dongsik KONG ,  Jihye KWON ,  Junsoo KIM ,  Junbum LEE

IPC: H01L29/423 ,  H01L29/78 ,  H10B12/00

Abstract: An integrated circuit device includes a substrate having formed therein a word line trench extending long in a first horizontal direction, a gate dielectric film covering an inner surface of the word line trench, a word line on the gate dielectric film, the word line filling a lower space of the word line trench and extending long in the first horizontal direction, an insulating capping pattern on the word line, the insulating capping pattern filling an upper space of the word line trench and extending long in the first horizontal direction, and at least one ferroelectric layer arranged at a top portion of the word line and including a first sidewall in contact with the gate dielectric film.

公开(公告)号：US20240251548A1

公开(公告)日：2024-07-25

申请号：US18454261

申请日：2023-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeyoon LEE ,  Junsoo KIM ,  Daehyun MOON

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/053 ,  H10B12/34

Abstract: A semiconductor device includes an active pattern extending along a first direction, and first and second word lines intersecting the active pattern. The active pattern includes a center active portion between the first and second word lines. The center active portion includes a center portion extending from the first word line to the second word line, a first center protrusion protruding from one side surface of the center portion in a second direction intersecting the first direction, and a second center protrusion protruding from another side surface of the center portion in an opposite direction to the second direction. The first center protrusion extends from the first word line along the first direction. The second center protrusion extends from the second word line along an opposite direction to the first direction.

公开(公告)号：US20210005506A1

公开(公告)日：2021-01-07

申请号：US16722622

申请日：2019-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyujin KIM ,  Hui-Jung KIM ,  Junsoo KIM ,  Sangho LEE ,  Jae-Hwan CHO ,  Yoosang HWANG

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L27/108

Abstract: A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.

公开(公告)号：US20200227418A1

公开(公告)日：2020-07-16

申请号：US16732925

申请日：2020-01-02

Applicant: Samsung Electronics Co., ltd.

Inventor： Hui-Jung KIM ,  Min Hee CHO ,  Junsoo KIM ,  Taehyun An ,  Dongsoo Woo ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

Abstract: A semiconductor memory device includes a stack structure having a plurality of layers vertically stacked on a substrate, each layer including, a first bit line and a gate line extending in a first direction, a first semiconductor pattern extending in a second direction between the first bit line and the gate line, the second direction intersecting the first direction, and a second semiconductor pattern adjacent to the gate line across a first gate insulating layer, the second semiconductor pattern extending in the first direction, a first word line adjacent to the first semiconductor pattern and vertically extending in a third direction from the substrate, a second bit line connected to an end of the second semiconductor pattern and vertically extending in the third direction from the substrate, and a second word line connected to another end of the second semiconductor pattern and vertically extending in the third direction.

公开(公告)号：US20180158918A1

公开(公告)日：2018-06-07

申请号：US15868620

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin LEE ,  Junsoo KIM ,  Moonyoung JEONG ,  Satoru YAMADA ,  Dongsoo WOO ,  Jiyoung KIM

IPC: H01L29/40 ,  H01L27/108 ,  H01L29/423

CPC classification number: H01L29/402 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/088 ,  H01L27/10876 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78639 ,  H01L29/78696

Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

公开(公告)号：US20180158826A1

公开(公告)日：2018-06-07

申请号：US15661121

申请日：2017-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Hee CHO ,  Satoru YAMADA ,  Junsoo KIM ,  Honglae PARK ,  Wonsok LEE ,  Namho JEON

IPC: H01L27/108 ,  H01L29/20 ,  H01L29/161

CPC classification number: H01L27/10805 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/161 ,  H01L29/20

Abstract: A semiconductor memory device includes a substrate having an active region, word lines extending across the active region, a bit line on the active region between the word lines, a bit line node contact between the bit line and the active region, and a storage node contact on an end portion of the active region, wherein one or more of the bit line node contact or the storage node contact include silicon germanium.