公开(公告)号：US20190103407A1

公开(公告)日：2019-04-04

申请号：US16038052

申请日：2018-07-17

申请人： Samsung Electronics Co., Ltd.

发明人： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

IPC分类号： H01L27/108

CPC分类号： H01L27/10805 ,  H01L27/0688 ,  H01L27/1085 ,  H01L28/86

摘要： Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

公开(公告)号：US20200111793A1

公开(公告)日：2020-04-09

申请号：US16707019

申请日：2019-12-09

申请人： Samsung Electronics Co., Ltd.

发明人： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

IPC分类号： H01L27/108 ,  H01L49/02 ,  H01L27/06

摘要： Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

公开(公告)号：US20170243973A1

公开(公告)日：2017-08-24

申请号：US15391888

申请日：2016-12-28

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sungsam LEE ,  Junsoo KIM ,  Hyoshin AHN ,  Satoru YAMADA ,  Joohyun JEON ,  MoonYoung JEONG ,  Chunhyung CHUNG ,  Min Hee CHO ,  Kyo-Suk CHAE ,  Eunae CHOI

IPC分类号： H01L29/78 ,  H01L29/04 ,  H01L29/423

CPC分类号： H01L29/7827 ,  H01L28/00 ,  H01L29/045 ,  H01L29/4236

摘要： A semiconductor device including a semiconductor substrate including a trench, the semiconductor substrate having a crystal structure; and an insulating layer covering an inner sidewall of the trench, wherein the inner sidewall of the trench has at least one plane included in a {320} family of planes of the crystal structure or at least one plane similar to the {320} family of planes.

公开(公告)号：US20160308000A1

公开(公告)日：2016-10-20

申请号：US15194066

申请日：2016-06-27

申请人： Samsung Electronics Co., Ltd.

发明人： Junsoo KIM ,  Dongjin LEE ,  Dongsoo WOO ,  Jun-Bum LEE ,  SANG-IL HAN

IPC分类号： H01L29/06 ,  H01L27/24 ,  H01L27/108 ,  H01L27/22 ,  H01L29/51 ,  H01L29/49

CPC分类号： H01L29/0653 ,  H01L27/088 ,  H01L27/10805 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/228 ,  H01L27/2436 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： A semiconductor device may include a semiconductor substrate including an active region defined by a trench, a device isolation layer provided in the trench to surround the active region, a gate electrode extending in a direction crossing the active region, and formed on the active region and the device isolation layer, and a gate insulating layer between the active region and the gate electrode. The active region may have a first conductivity type, and the device isolation layer may include a first silicon oxide layer on an inner surface of the first trench and a different layer, selected from one of first metal oxide layer and a negatively-charged layer, on the first silicon oxide layer.

公开(公告)号：US20160240619A1

公开(公告)日：2016-08-18

申请号：US15011820

申请日：2016-02-01

申请人： Samsung Electronics Co., Ltd.

发明人： Dongjin LEE ,  Junsoo KIM ,  Moonyoung JEONG ,  Satoru YAMADA ,  Dongsoo WOO ,  Jiyoung KIM

IPC分类号： H01L29/40 ,  H01L29/423 ,  H01L27/088

CPC分类号： H01L29/402 ,  H01L27/088 ,  H01L27/10876 ,  H01L29/42392

摘要： A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

摘要翻译： 半导体器件可以包括被配置为在衬底中限定有源区的器件隔离区，设置在有源区中的有源栅极结构以及设置在器件隔离区中的场栅结构。 场栅结构可以包括栅极导电层。 有源栅极结构可以包括上有源栅极结构，其包括形成在上有源栅极结构下方并与上有源栅极结构垂直间隔开的栅极导电层和下有源栅极结构。 下部有源栅极结构可以包括栅极导电层。 场栅结构的栅极导电层的顶表面位于比上有源栅极结构的栅极导电层的底表面更低的水平处。

公开(公告)号：US20240268098A1

公开(公告)日：2024-08-08

申请号：US18510949

申请日：2023-11-16

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Junsoo KIM ,  Dongsik KONG ,  Jihye KWON ,  Junbum LEE ,  Sungho JANG

IPC分类号： H10B12/00 ,  H01L29/66 ,  H01L29/78

CPC分类号： H10B12/315 ,  H01L29/66666 ,  H01L29/7827 ,  H10B12/053 ,  H10B12/34

摘要： A semiconductor device includes a first active pattern protruding from a substrate; a gate structure including a gate insulation layer and a gate pattern laterally stacked on a first sidewall of the first active pattern, the gate pattern facing the first sidewall of the first active pattern and extending a first direction parallel to an upper surface of the substrate; and first conductive patterns contacting the gate insulation layer and protruding from a sidewall of the gate structure. The first conductive patterns may be disposed to face second and third sidewalls in the first direction of the first active pattern, and first conductive patterns may be spaced apart from the first active pattern.

公开(公告)号：US20210057416A1

公开(公告)日：2021-02-25

申请号：US17090419

申请日：2020-11-05

申请人： Samsung Electronics Co., Ltd.

发明人： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

IPC分类号： H01L27/108 ,  H01L27/06 ,  H01L49/02

摘要： Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

公开(公告)号：US20190198626A1

公开(公告)日：2019-06-27

申请号：US16288910

申请日：2019-02-28

申请人： Samsung Electronics Co., Ltd.

发明人： Dongjin LEE ,  Junsoo KIM ,  Moonyoung JEONG ,  Satoru YAMADA ,  Dongsoo WOO ,  Jiyoung KIM

IPC分类号： H01L29/40 ,  H01L27/108 ,  H01L29/66 ,  B82Y10/00 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L21/84

CPC分类号： H01L29/402 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/088 ,  H01L27/10876 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78639 ,  H01L29/78696

摘要： A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

公开(公告)号：US20240251548A1

公开(公告)日：2024-07-25

申请号：US18454261

申请日：2023-08-23

申请人： Samsung Electronics Co., Ltd.

发明人： Taeyoon LEE ,  Junsoo KIM ,  Daehyun MOON

IPC分类号： H10B12/00

CPC分类号： H10B12/488 ,  H10B12/053 ,  H10B12/34

摘要： A semiconductor device includes an active pattern extending along a first direction, and first and second word lines intersecting the active pattern. The active pattern includes a center active portion between the first and second word lines. The center active portion includes a center portion extending from the first word line to the second word line, a first center protrusion protruding from one side surface of the center portion in a second direction intersecting the first direction, and a second center protrusion protruding from another side surface of the center portion in an opposite direction to the second direction. The first center protrusion extends from the first word line along the first direction. The second center protrusion extends from the second word line along an opposite direction to the first direction.

公开(公告)号：US20210005506A1

公开(公告)日：2021-01-07

申请号：US16722622

申请日：2019-12-20

申请人： Samsung Electronics Co., Ltd.

发明人： Kyujin KIM ,  Hui-Jung KIM ,  Junsoo KIM ,  Sangho LEE ,  Jae-Hwan CHO ,  Yoosang HWANG

IPC分类号： H01L21/762 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L27/108

摘要： A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.