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    SEMICONDUCTOR MEMORY DEVICES
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20200111793A1

    公开(公告)日：2020-04-09

    申请号：US16707019

    申请日：2019-12-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L49/02 ,  H01L27/06

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

    SEMICONDUCTOR DEVICE HAVING BURIED GATE STRUCTURE AND METHOD OF FABRICATING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE HAVING BURIED GATE STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
    具有盖式结构的半导体器件及其制造方法

    公开(公告)号：US20160240619A1

    公开(公告)日：2016-08-18

    申请号：US15011820

    申请日：2016-02-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongjin LEE ,  Junsoo KIM ,  Moonyoung JEONG ,  Satoru YAMADA ,  Dongsoo WOO ,  Jiyoung KIM

    IPC: H01L29/40 ,  H01L29/423 ,  H01L27/088

    CPC classification number: H01L29/402 ,  H01L27/088 ,  H01L27/10876 ,  H01L29/42392

    Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

    Abstract translation: 半导体器件可以包括被配置为在衬底中限定有源区的器件隔离区，设置在有源区中的有源栅极结构以及设置在器件隔离区中的场栅结构。 场栅结构可以包括栅极导电层。 有源栅极结构可以包括上有源栅极结构，其包括形成在上有源栅极结构下方并与上有源栅极结构垂直间隔开的栅极导电层和下有源栅极结构。 下部有源栅极结构可以包括栅极导电层。 场栅结构的栅极导电层的顶表面位于比上有源栅极结构的栅极导电层的底表面更低的水平处。

    SEMICONDUCTOR DEVICES
    6.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240268098A1

    公开(公告)日：2024-08-08

    申请号：US18510949

    申请日：2023-11-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junsoo KIM ,  Dongsik KONG ,  Jihye KWON ,  Junbum LEE ,  Sungho JANG

    IPC: H10B12/00 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H10B12/315 ,  H01L29/66666 ,  H01L29/7827 ,  H10B12/053 ,  H10B12/34

    Abstract: A semiconductor device includes a first active pattern protruding from a substrate; a gate structure including a gate insulation layer and a gate pattern laterally stacked on a first sidewall of the first active pattern, the gate pattern facing the first sidewall of the first active pattern and extending a first direction parallel to an upper surface of the substrate; and first conductive patterns contacting the gate insulation layer and protruding from a sidewall of the gate structure. The first conductive patterns may be disposed to face second and third sidewalls in the first direction of the first active pattern, and first conductive patterns may be spaced apart from the first active pattern.

    SEMICONDUCTOR MEMORY DEVICES
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20210057416A1

    公开(公告)日：2021-02-25

    申请号：US17090419

    申请日：2020-11-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

    SEMICONDUCTOR MEMORY DEVICE
    9.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240341083A1

    公开(公告)日：2024-10-10

    申请号：US18493196

    申请日：2023-10-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jun-Bum LEE ,  Dongsik KONG ,  Jihye KWON ,  Junsoo KIM ,  Jae Hyun CHOI ,  Hyun Seung CHOI

    IPC: H10B12/00

    CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/482

    Abstract: Active regions defined by device isolation layer are provided on a substrate. A word line crossing the active regions and a gate dielectric layer between the word line and the active regions are provided. A capping insulating pattern covering an upper surface of the word line and a bit line on the word line are provided. The word line may include a first conductive pattern and a second conductive pattern on the first conductive pattern. The first conductive pattern may include a first metal element. The second conductive pattern may include the first metal element, a work function adjustment element, and a diffusion barrier element. An atomic radius of the diffusion barrier element may be smaller than an atomic radius of the first metal element.

    SEMICONDUCTOR DEVICES
    10.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240268103A1

    公开(公告)日：2024-08-08

    申请号：US18511000

    申请日：2023-11-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junsoo KIM ,  Sungho JANG

    IPC: H10B12/00

    CPC classification number: H10B12/485 ,  H10B12/315 ,  H10B12/482

    Abstract: A semiconductor device includes a first active pattern protruding from a substrate and extending in a first direction parallel to an upper surface of the substrate; first and second recesses crossing the first active pattern in a second direction perpendicular to the first direction; a first gate structure in the first recess, and including a first gate oxide layer, a first gate pattern and a first capping pattern; a second gate structure in the second recess, and including a second gate oxide layer, a second gate pattern and a second capping pattern; a first metal liner pattern surrounding a portion of a sidewall of the first active pattern, and directly contacting a sidewall of the first gate pattern; and a second metal liner pattern surrounding a portion of the sidewall of the first active pattern, and directly contacting a sidewall of the second gate pattern.

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