公开(公告)号：US20210153300A1

公开(公告)日：2021-05-20

申请号：US17137969

申请日：2020-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinhong KIM ,  Seyun KIM ,  Haengdeog KOH ,  Doyoon KIM ,  Hajin KIM ,  Soichiro MIZUSAKI ,  Minjong BAE ,  Changsoo LEE

IPC: H05B1/02 ,  H05B3/26

Abstract: Provided are a structure, a planar heater including the same, a heating device including the planar heater, and a method of preparing the structure. The structure includes a metal substrate, an insulating layer disposed on the metal substrate, an electrode layer disposed on the insulating layer, and an electrically conductive layer disposed on the electrode layer, wherein a difference in a coefficient of thermal expansion (CTE) between the metal substrate and the insulating layer is 4 parts per million per degree Kelvin change in temperature (ppm/K) or less.

公开(公告)号：US20200350497A1

公开(公告)日：2020-11-05

申请号：US16691818

申请日：2019-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungho YOON ,  Soichiro MIZUSAKI ,  Youngjin CHO

IPC: H01L45/00

Abstract: A variable resistance memory device includes a first conductive line extending in a first direction, a second conductive line extending in a second direction, the second direction intersecting the first direction on the first conductive line, a fixed resistance layer between the first conductive line and the second conductive line, and a variable resistance layer between the first conductive line and the second conductive line, wherein the fixed resistance layer and the variable resistance layer are electrically connected in parallel to each other between the first conductive line and the second conductive line.

公开(公告)号：US20190037644A1

公开(公告)日：2019-01-31

申请号：US16045834

申请日：2018-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinhong KIM ,  Seyun KIM ,  Haengdeog KOH ,  Doyoon KIM ,  Hajin KIM ,  Soichiro MIZUSAKI ,  Minjong BAE ,  Changsoo LEE

IPC: H05B1/02

Abstract: Provided are a structure, a planar heater including the same, a heating device including the planar heater, and a method of preparing the structure. The structure includes a metal substrate, an insulating layer disposed on the metal substrate, an electrode layer disposed on the insulating layer, and an electrically conductive layer disposed on the electrode layer, wherein a difference in a coefficient of thermal expansion (CTE) between the metal substrate and the insulating layer is 4 parts per million per degree Kelvin change in temperature (ppm/K) or less.

公开(公告)号：US20180099487A1

公开(公告)日：2018-04-12

申请号：US15723339

申请日：2017-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haengdeog Koh ,  Doyoon Kim ,  Seyun Kim ,  Jinhong Kim ,  Hajin Kim ,  Soichiro MIZUSAKI ,  Minjong Bae ,  Hiesang Sohn ,  Changsoo Lee

IPC: B32B17/10 ,  C01G55/00 ,  C03C8/02

CPC classification number: B32B17/10174 ,  B32B17/10944 ,  B82Y30/00 ,  C01G55/004 ,  C01P2002/02 ,  C01P2004/03 ,  C01P2004/50 ,  C01P2004/51 ,  C01P2004/62 ,  C01P2004/64 ,  C03C3/093 ,  C03C8/02 ,  C03C14/002 ,  C03C14/006 ,  C03C17/008 ,  C03C2214/02 ,  C03C2214/16 ,  C03C2217/452 ,  C03C2217/48

Abstract: A composite material structure including a matrix material layer; and a plurality of one-dimensional nanostructure distributed in the matrix material layer and having an electrical conductivity which is greater than an electrical conductivity of the matrix material layer, wherein the plurality of one-dimensional nanostructures includes a first one-dimensional nanostructure and a second one-dimensional nanostructure in contact with each other.

公开(公告)号：US20220310827A1

公开(公告)日：2022-09-29

申请号：US17459527

申请日：2021-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yumin KIM ,  Doyoon KIM ,  Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI ,  Youngjin CHO

IPC: H01L29/68 ,  H01L27/115

Abstract: Disclosed are a memory device including a vertical stack structure and a method of manufacturing the memory device. The memory device includes an insulating structure having a shape including a first surface and a protrusion portion protruding in a first direction from the first surface, a recording material layer covering the protrusion portion along a protruding shape of the protrusion portion and extending to the first surface on the insulating structure a channel layer on the recording material layer along a surface of the recording material layer, a gate insulating layer on the channel layer, and a gate electrode formed at a location on the gate insulating layer to face a second surface which is a protruding upper surface of the protrusion portion, wherein a void exists between the gate electrode and the insulating structure, defined by the insulating structure and the recording material layer.

公开(公告)号：US20220077235A1

公开(公告)日：2022-03-10

申请号：US17317154

申请日：2021-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yumin KIM ,  Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI ,  Youngjin CHO

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory device may include an insulating structure including a first surface and a protrusion portion protruding from the first surface in a first direction, a recording material layer on the insulating structure and extending along a protruding surface of the protrusion portion to cover the protrusion portion and extending onto the first surface of the insulating structure, a channel layer on the recording material layer and extending along a surface of the recording material layer, a gate insulating layer on the channel layer; and a gate electrode formed on the gate insulating layer at a location facing a second surface of the insulating structure. The second surface of the insulating structure may be a protruding upper surface of the protrusion portion.

公开(公告)号：US20210350851A1

公开(公告)日：2021-11-11

申请号：US17385263

申请日：2021-07-26

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Jungho YOON ,  Cheol Seong HWANG ,  Soichiro MIZUSAKI ,  Youngjin CHO

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: A nonvolatile memory device and a method of operating the same are provided. The nonvolatile memory device may include a memory cell array having a vertical stack-type structure, a control logic, and a bit line. The memory cell array may include memory cells that each include corresponding portions of a semiconductor layer and a resistance change layer. The control logic, in a read operation, may be configured to apply a first voltage to a non-select memory cell and a second voltage to a non-select memory cell. The first voltage turns on current only in the semiconductor layer portion of the non-select memory cell. The second voltage turns on current in both the semiconductor layer and resistance change layer portions of the select memory cell. The bit line may be configured to apply a read voltage to the select memory cell during the read operation.

公开(公告)号：US20210035641A1

公开(公告)日：2021-02-04

申请号：US16775424

申请日：2020-01-29

Applicant: Samsung Electronics Co. Ltd.

Inventor： Jungho YOON ,  Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI ,  Youngjin CHO

IPC: G11C16/10 ,  H01L27/11582 ,  G11C16/24 ,  G11C16/04 ,  G11C16/26

Abstract: Provided are a non-volatile memory device and an operating method thereof. The non-volatile memory device includes a memory cell array having a vertically stacked structure, a bit line for applying a programming voltage to the memory cell array, and a control logic. The memory cell array includes memory cells that each include a corresponding portion of a semiconductor layer and a corresponding portion of a resistance layer. The memory cells include a non-selected memory cell, a compensation memory cell, and a selected memory cell. The control logic is configured to apply an adjusted program voltage to the selected memory cell, based on applying a first voltage to the compensation memory cell, a second voltage to the selected memory cell, and a third voltage to the non-selected memory cell. The adjusted program voltage may be dropped compared to the programming voltage due to the compensation memory cell.

公开(公告)号：US20180136181A1

公开(公告)日：2018-05-17

申请号：US15810229

申请日：2017-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjong Bae ,  Jinhong Kim ,  Hajin Kim ,  Haengdeog Koh ,  Doyoon Kim ,  Seyun Kim ,  Soichiro MIZUSAKI ,  Hiesang Sohn ,  Changsoo Lee

IPC: G01N33/00 ,  H01B1/14 ,  H01B5/14

CPC classification number: G01N33/0027 ,  G08B17/103 ,  H01B1/14 ,  H01B3/004 ,  H01B3/087 ,  H01B5/14

Abstract: A composite filler structure includes a substrate, a filler layer spaced apart from the substrate and comprising a matrix material layer and a plurality of conductive filler particles, an electrode in contact with the filler layer and configured to provide an electrical signal to the filler layer, and an insulating layer between the substrate and the electrode, and including an alkali oxide in an amount of about 7 weight percent or less, based on a total weight of the composite filler structure.

公开(公告)号：US20160293290A1

公开(公告)日：2016-10-06

申请号：US15047790

申请日：2016-02-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soichiro MIZUSAKI ,  Sang Eui LEE ,  Won Suk CHANG ,  In Taek HAN

IPC: H01B1/24

CPC classification number: H01B1/24 ,  B82Y30/00 ,  Y10S977/752 ,  Y10S977/932

Abstract: A composition for preparing an electrically conductive composite includes, based on the total weight of the composition: about 37 weight percent to about 84 weight percent of an epoxy; about 0.001 weight percent to about 22 weight percent of an electrically conductive filler; and about 15 weight percent to about 45 weight percent of a thermoplastic resin, wherein the thermoplastic resin is a liquid at about 25° C., is miscible with the epoxy, and forms a domain upon heat curing that is phase-separated from the epoxy and the electrically conductive inorganic filler. Also composites prepared therefrom and an electronic device including the same.