公开(公告)号：US07028196B2

公开(公告)日：2006-04-11

申请号：US10319667

申请日：2002-12-13

申请人： Donald C. Soltis, Jr. ,  Samuel Naffziger

发明人： Donald C. Soltis, Jr. ,  Samuel Naffziger

IPC分类号： G06F1/26 ,  G06F12/00

CPC分类号： G06F1/3287 ,  G06F1/206 ,  G06F1/3203 ,  Y02D10/16 ,  Y02D10/171

摘要： A processor integrated circuit has at least one processor and two or more levels of cache memory. A first power connection provides power to the processor and lower level cache, which form a first power domain. The integrated circuit has a second power connection providing power to upper level cache of the circuit, forming a second power domain. There may be additional power connections to the integrated circuit, forming additional power domains, such as periphery or memory-interface power.

摘要翻译： 处理器集成电路具有至少一个处理器和两个或多个级别的高速缓冲存储器。 第一电源连接为处理器和下级缓存提供电力，其形成第一电源域。 集成电路具有向电路的高级缓存提供电力的第二电力连接，形成第二电源域。 可能存在与集成电路的额外电源连接，形成额外的电源域，例如外围或存储器接口电源。

公开(公告)号：US06922783B2

公开(公告)日：2005-07-26

申请号：US10050735

申请日：2002-01-16

申请人： Derek Knee ,  Samuel Naffziger

发明人： Derek Knee ,  Samuel Naffziger

IPC分类号： G06F12/08 ,  G06F1/26 ,  G06F1/32 ,  G06F15/16 ,  G06F15/78 ,  H04L9/32

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

摘要： A multiple processor integrated circuit has a first processor-first level cache combination powered by a first power terminal, and a second processor-first level cache combination powered by a second power terminal. There is common circuitry coupled to each processor-cache combination. In a particular embodiment, the processor-cache combinations are capable of receiving independently controlled power over the power terminals.

摘要翻译： 多处理器集成电路具有由第一电源终端供电的第一处理器级高速缓存组合和由第二电源终端供电的第二处理器级高速缓存组合。 存在耦合到每个处理器 - 缓存组合的公共电路。 在特定实施例中，处理器 - 高速缓存组合能够通过电源终端接收独立控制的电力。

公开(公告)号：US20050076259A1

公开(公告)日：2005-04-07

申请号：US10679786

申请日：2003-10-06

申请人： Timothy Fischer ,  Samuel Naffziger

发明人： Timothy Fischer ,  Samuel Naffziger

IPC分类号： G06F1/04 ,  G06F1/08 ,  G06F1/12

CPC分类号： G06F1/12 ,  G06F1/08

摘要： In one embodiment, a central processing unit (CPU) includes multiple clock zones. Each clock zone includes at least one sensor that generates a signal indicative of a power supply voltage within the clock zone, a clock generator for providing a variable frequency clock to the clock zone, a first controller for controlling a frequency of operation of the clock generator in response to the at least one sensor, wherein the first controller further controls the frequency of operation in response to communication of frequency adjustments from first controllers in other clock zones within one cycle of latency, and a second controller that provides an overdrive signal, that is combined with adjustment signals from the first controller for the clock generator, in response to communication of frequency adjustments from other clock zones beyond one cycle of latency.

摘要翻译： 在一个实施例中，中央处理单元（CPU）包括多个时钟区域。 每个时钟区域包括至少一个传感器，其生成指示时钟区域内的电源电压的信号，用于向时钟区域提供可变频率时钟的时钟发生器，用于控制时钟发生器的操作频率的第一控制器 响应于所述至少一个传感器，其中所述第一控制器响应于来自等待时间的一个周期内的其他时钟区域中的第一控制器的频率调整的通信，以及提供过驱动信号的第二控制器，来控制所述操作频率， 响应于来自其他时钟区域的频率调整的通信超过一个等待时间周期，与来自时钟发生器的第一控制器的调整信号组合。

公开(公告)号：US20050040858A1

公开(公告)日：2005-02-24

申请号：US10646935

申请日：2003-08-22

申请人： Samuel Naffziger

发明人： Samuel Naffziger

IPC分类号： G01R31/30 ,  G01R31/28 ,  G01R31/317 ,  G06F1/04 ,  H03K5/06 ,  H03K19/0185 ,  H03K19/00

CPC分类号： G06F1/04 ,  G01R31/31725 ,  H03K5/06 ,  H03K19/018585

摘要： Systems and methods are disclosed for controlling an associated circuit. A clock waveform that transitions between normally high and low levels over a cycle in a first operating mode is provided to the associated circuit. The clock waveform is modified to include an intermediate level between the normally high and low levels over a cycle in a second operating mode.

摘要翻译： 公开了用于控制相关电路的系统和方法。 在相关联的电路中提供在第一操作模式中在一个周期内在正常高电平和低电平之间转换的时钟波形。 时钟波形被修改为在第二操作模式中在一个周期内包括正常高电平和低电平之间的中间电平。

公开(公告)号：US06640283B2

公开(公告)日：2003-10-28

申请号：US10050736

申请日：2002-01-16

申请人： Samuel Naffziger ,  Wayne Kever

发明人： Samuel Naffziger ,  Wayne Kever

IPC分类号： G06F1300

CPC分类号： G06F12/0802 ,  G06F2212/401

摘要： A compression engine for a cache memory subsystem has a pointer into cache tag memory and cache data memory and an interface coupled to the pointer and capable of being coupled to cache tag memory, and cache data memory. The interface reads tag information and uncompressed data from the cache and writes modified tag information and compressed data to the cache. The compression engine also has compression logic for generating compressed data and generate compression successful information, and tag line update circuitry for generating modified tag information according to the compression successful information and the tag information. Also disclosed is a cache subsystem for a computer system embodying the compression engine, and a method of compressing cache using the compression engine.

公开(公告)号：US20190067152A1

公开(公告)日：2019-02-28

申请号：US15686558

申请日：2017-08-25

申请人： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

发明人： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC分类号： H01L23/367 ,  H01L25/065 ,  H01L25/00

摘要： Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

公开(公告)号：US07447919B2

公开(公告)日：2008-11-04

申请号：US10818974

申请日：2004-04-06

申请人： Steven F. Liepe ,  Samuel Naffziger

发明人： Steven F. Liepe ,  Samuel Naffziger

IPC分类号： G06F1/00 ,  G06F11/00

CPC分类号： H03K19/0008 ,  G06F11/00

摘要： Techniques are disclosed for increasing reliability of an integrated circuit. In one embodiment, an integrated circuit includes core chip circuitry. The integrated circuit includes means for increasing a power supply voltage V provided to the core chip circuitry, such as by increasing the voltage V to a maximum value. The integrated circuit also includes means for identifying a clock frequency F for which F

摘要翻译： 公开了用于增加集成电路的可靠性的技术。 在一个实施例中，集成电路包括核心芯片电路。 集成电路包括用于增加提供给核心芯片电路的电源电压V的装置，例如通过将电压V增加到最大值。 集成电路还包括用于识别其中C是开关电容的时钟频率F的装置，其中P < max 是核心芯片电路的预定最大功耗。 集成电路还包括用于向电路提供具有频率F的时钟信号的装置。

公开(公告)号：US20060279343A1

公开(公告)日：2006-12-14

申请号：US11152274

申请日：2005-06-13

申请人： Samuel Naffziger

发明人： Samuel Naffziger

IPC分类号： H03K3/356

CPC分类号： H03K3/0375 ,  H03K3/356104

摘要： In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. A low-pass filter is placed between the output of a forward inverter and the inputs of a feedback keeper. The first and second outputs of the low-pass filter are connected to first and second inputs respectively of the feedback keeper. The only type of diffusion connected to the first output of the low-pass filter is a P-type diffusion. The only type of diffusion connected to the second output of the low-pass filter is an N-type diffusion. The feedback keeper is connected to an input of the forward inverter.

摘要翻译： 在优选实施例中，本发明提供了用于减少锁存器中的软错误事件的电路和方法。 在正向逆变器的输出端和反馈保持器的输入端之间放置一个低通滤波器。 低通滤波器的第一和第二输出分别连接到反馈保持器的第一和第二输入端。 连接到低通滤波器的第一输出的唯一类型的扩散是P型扩散。 连接到低通滤波器的第二输出的唯一类型的扩散是N型扩散。 反馈控制器连接到正向逆变器的输入。

公开(公告)号：US20060248367A1

公开(公告)日：2006-11-02

申请号：US11118600

申请日：2005-04-29

申请人： Timothy Fischer ,  Samuel Naffziger ,  Benjamin Patella

发明人： Timothy Fischer ,  Samuel Naffziger ,  Benjamin Patella

IPC分类号： G06F1/12

CPC分类号： G06F1/12

摘要： Systems and methods for implementing count calibration for synchronous data transfer between clock domains are disclosed. An exemplary system may include a count calibration circuit for determining latency between an early clock domain and a late clock domain. The system may also include a data path configurable for synchronous data transfer between clock domains based at least in part on the latency.

摘要翻译： 公开了用于实现时钟域之间同步数据传输的计数校准的系统和方法。 示例性系统可以包括用于确定早期时钟域和后期时钟域之间的等待时间的计数校准电路。 系统还可以包括至少部分地基于等待时间来配置用于时钟域之间的同步数据传输的数据路径。

公开(公告)号：US20060069928A1

公开(公告)日：2006-03-30

申请号：US10951179

申请日：2004-09-27

申请人： Bradley Winick ,  Samuel Naffziger

发明人： Bradley Winick ,  Samuel Naffziger

IPC分类号： G06F1/26

CPC分类号： G06F1/305

摘要： Systems, methodologies, media, and other embodiments associated with detecting and responding to a degradation of a direct current provided to a frequency scalable processor are described. One exemplary frequency scalable processor includes a voltage regulating logic configured to request that a direct current having a reference voltage be provided to the processor. The example processor may also include a logic for detecting whether the voltage matches the reference voltage to within a desired tolerance and to selectively store processor state and/or data based on the detecting.