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公开(公告)号：US12046297B2
公开(公告)日：2024-07-23
申请号：US17824350
申请日：2022-05-25
Applicant: SanDisk Technologies LLC
Inventor： Peng Wang , Jia Li , Behrang Bagheri , Keyur Payak , Bo Lei , Long Pham , Jun Wan
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/32 , H10B41/27 , H10B43/27
Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.
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12.发明公开公开(公告)号：US20230377655A1
公开(公告)日：2023-11-23
申请号：US17747088
申请日：2022-05-18
Applicant: SanDisk Technologies LLC
Inventor： Huiwen Xu , Nidhi Agrawal , Zhenni Wan , Bo Lei , Jun Wan
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/26 , H01L27/11556
Abstract: The memory device that includes a memory block memory cells arranged in word lines. A controller is in electrical communication with the memory cells and is configured to program the memory cells to a first set of data states in a first programming pass and then to a greater second set of data states in a second programming pass. During programming of a first set of memory cells in at least one of the first and second programming passes, the controller is further configured to determine programming statuses of a second set of memory cells that is adjacent the first set of memory cells. The controller is further configured to read the first set of memory cells using a read voltage that is adjusted from a base read voltage based on the determined programming statuses of the second set of memory cells.
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公开(公告)号：US20230124371A1
公开(公告)日：2023-04-20
申请号：US17502398
申请日：2021-10-15
Applicant: SanDisk Technologies LLC
Abstract: The memory device includes a control circuitry that is communicatively coupled to memory cells are arranged in a plurality of word lines. The control circuitry is configured to perform a first programming pass on a selected word line. The first programming pass includes a plurality of programming loops, each of which includes the application of a programming pulse (Vpgm). The programming pulse voltage is increased between programming loops of the first programming pass by a step size. The step size is a first step size between two programming loops of the first programming pass and is a second step size that is different than the first step size between two other programming loops of the first programming pass. The control circuitry is also configured to perform a second programming pass to further program the memory cells of the selected word line to the plurality of data states.
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公开(公告)号：US20200211652A1
公开(公告)日：2020-07-02
申请号：US16236792
申请日：2018-12-31
Applicant: SanDisk Technologies LLC
Inventor： Jianzhi Wu , Xiang Yang , Jun Wan
Abstract: Example techniques that mitigate against memory hole shorts during an erase operation for memory cells in a string include an example method in which, during an erase operation, erase pulses are applied to the word lines of the memory string and terminated at different times based. In some instances, the erase pulses applied to the word lines of the memory string are terminated based on the temperature of the memory cells of the memory string. In further implementations, the erase pulses applied to the word lines of the memory string are boosted for different times depending on the location of the word line along the memory string during the erase operation.
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公开(公告)号：US20180254090A1
公开(公告)日：2018-09-06
申请号：US15816546
申请日：2017-11-17
Applicant: SanDisk Technologies LLC
Inventor： Deepanshu Dutta , Idan Alrod , Huai-Yuan Tseng , Amul Desai , Jun Wan , Ken Cheah , Sarath Puthenthermadam
CPC classification number: G11C16/3413 , G11C8/08 , G11C11/5642 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/3445 , G11C16/3459 , G11C29/021 , G11C29/028 , G11C2029/1202
Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.
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Patent Agency Ranking
公开(公告)号：US20180046231A1
公开(公告)日：2018-02-15
申请号：US15237139
申请日：2016-08-15
Applicant: SanDisk Technologies LLC
Inventor： Deepak Raghu , Pao-Ling Koh , Philip Reusswig , Chris Nga Yee Yip , Jun Wan , Yan Li
CPC classification number: G06F1/206 , G06F1/3225 , G06F1/3275 , G06F3/0616 , G06F3/0653 , G06F3/0688
Abstract: A storage device with a memory may modify throttling to reduce cross temperature effects. The decision to throttle may be based on a memory device temperature (i.e. temperature throttling) or may be based on the memory device's health, usage, or performance (e.g. hot count or bit error rate). Temperature throttling may be implemented that considers the memory device's health, usage, or performance (e.g. hot count or bit error rate). Likewise, throttling based on the memory device's health, usage, or performance may utilize the memory device's temperature to optimize throttling time. For example, a test mode matrix (TMM) may be modified to depend on temperature.
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17.发明授权公开(公告)号：US12057169B2
公开(公告)日：2024-08-06
申请号：US17747088
申请日：2022-05-18
Applicant: SanDisk Technologies LLC
Inventor： Huiwen Xu , Nidhi Agrawal , Zhenni Wan , Bo Lei , Jun Wan
Abstract: The memory device that includes a memory block memory cells arranged in word lines. A controller is in electrical communication with the memory cells and is configured to program the memory cells to a first set of data states in a first programming pass and then to a greater second set of data states in a second programming pass. During programming of a first set of memory cells in at least one of the first and second programming passes, the controller is further configured to determine programming statuses of a second set of memory cells that is adjacent the first set of memory cells. The controller is further configured to read the first set of memory cells using a read voltage that is adjusted from a base read voltage based on the determined programming statuses of the second set of memory cells.
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公开(公告)号：US20230386580A1
公开(公告)日：2023-11-30
申请号：US17824350
申请日：2022-05-25
Applicant: SanDisk Technologies LLC
Inventor： Peng Wang , Jia Li , Behrang Bagheri , Keyur Payak , Bo Lei , Long Pham , Jun Wan
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/32 , H01L27/11556
Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.
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公开(公告)号：US11328780B1
公开(公告)日：2022-05-10
申请号：US17116579
申请日：2020-12-09
Applicant: SanDisk Technologies LLC
Abstract: Apparatuses and techniques are described for optimizing a program operation in a memory device in which groups of memory cells are programmed from checkpoint states to respective data states. In a first program pass, groups of memory cells are programmed to respective checkpoint states with verify tests. Each checkpoint state is associated with a set of data states. In a second program pass, the memory cells are programmed closer to their assigned data state with a specified number of program pulses. In a third program pass, the memory cells are programmed to their assigned data state by applying program pulses and performing verify tests. The number of checkpoint states and the number of data states associated with each checkpoint state can be optimized based on a spacing between the verify voltages of the data states.
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公开(公告)号：US10978160B2
公开(公告)日：2021-04-13
申请号：US16236792
申请日：2018-12-31
Applicant: SanDisk Technologies LLC
Inventor： Jianzhi Wu , Xiang Yang , Jun Wan
Abstract: Example techniques that mitigate against memory hole shorts during an erase operation for memory cells in a string include an example method in which, during an erase operation, erase pulses are applied to the word lines of the memory string and terminated at different times based. In some instances, the erase pulses applied to the word lines of the memory string are terminated based on the temperature of the memory cells of the memory string. In further implementations, the erase pulses applied to the word lines of the memory string are boosted for different times depending on the location of the word line along the memory string during the erase operation.
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