公开(公告)号：US11195820B2

公开(公告)日：2021-12-07

申请号：US16808128

申请日：2020-03-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Kirubakaran Periyannan ,  Jayavel Pachamuthu ,  Narendhiran Cr ,  Jay Dholakia ,  Everett Lyons, IV ,  Hoang Huynh ,  Dat Dinh

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/525

Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.

公开(公告)号：US11139276B2

公开(公告)日：2021-10-05

申请号：US16808128

申请日：2020-03-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Kirubakaran Periyannan ,  Jayavel Pachamuthu ,  Narendhiran Cr ,  Jay Dholakia ,  Everett Lyons, IV ,  Hoang Huynh ,  Dat Dinh

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/525

Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.

公开(公告)号：US10984883B1

公开(公告)日：2021-04-20

申请号：US16728447

申请日：2019-12-27

Applicant: SanDisk Technologies LLC

Inventor： Sowjanya Tungala ,  Sini Balakrishnan ,  Sowjanya Sunkavelli ,  Sridhar Yadala ,  Dat Tran ,  Loc Tu ,  Kirubakaran Periyannan

IPC: G11C29/44 ,  G11C29/00 ,  G11C29/18

Abstract: A memory management method includes identifying memory segments of a memory device. The method also includes identifying, for each memory segment, a number of faulty columns and determining a total number of faulty columns for the memory device. The method also includes, in response to a determination that the total number of faulty columns is greater than a threshold, identifying a memory segment having a highest number of faulty columns. The method also includes disabling the memory segment. Another method includes identifying, for each memory segment, a number of faulty memory blocks and determining a total number of faulty memory blocks. The method also includes, in response to a determination that the total number of faulty memory blocks is greater than a threshold, identifying a memory segment having a highest number of faulty memory blocks. The method also includes disabling the memory segment.

公开(公告)号：US10776277B2

公开(公告)日：2020-09-15

申请号：US15799643

申请日：2017-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Avinash Rajagiri ,  Shantanu Gupta ,  Jagdish Sabde ,  Ashish Ghai ,  Deepak Bharadwaj

IPC: G06F12/10 ,  G06F3/06 ,  G11C16/04 ,  G11C13/00 ,  G11C11/16 ,  G11C16/08 ,  G11C5/02 ,  G11C16/10 ,  G11C8/06 ,  G11C7/10

Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

公开(公告)号：US10276251B1

公开(公告)日：2019-04-30

申请号：US15851139

申请日：2017-12-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Sukhminder Singh Lobana ,  Kirubakaran Periyannan ,  Ankitkumar Babariya

IPC: G11C7/00 ,  G11C29/00 ,  G11C16/34 ,  G11C29/12

Abstract: A memory system performs verification when writing to memory. It is possible that the memory system may be missing some components (or components may be otherwise unavailable). To account for missing or unavailable components when performing verification, the memory system uses a pattern of data that includes a mask identifying the missing or unavailable components. The mask is used to force a predetermined result of the verification for the missing or unavailable portions of the memory structure so that results of the verification that correspond to the missing or unavailable components are not counted as errors.

公开(公告)号：US10242750B2

公开(公告)日：2019-03-26

申请号：US15610119

申请日：2017-05-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Shantanu Gupta ,  Avinash Rajagiri ,  Dongxiang Liao ,  Jagdish Sabde ,  Rajan Paudel

IPC: G11C29/12 ,  G11C7/10 ,  G11C7/22

Abstract: Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.

公开(公告)号：US11086539B2

公开(公告)日：2021-08-10

申请号：US16659353

申请日：2019-10-21

Applicant: SanDisk Technologies LLC

Inventor： Dat Tran ,  Loc Tu ,  Kirubakaran Periyannan

IPC: G06F3/06

Abstract: Consecutive logical block addresses (LBAs) are mapped to consecutive good blocks in a sequence of blocks in a memory device. For each bad block, a mapping process substitutes a next available good block. For a selected LBA, the mapping process determines a number X>1 of bad blocks before, and including, a corresponding block in the sequence, a number Y of bad blocks in the X blocks after the corresponding block in the sequence, and maps the LBA to a block which is X+Y blocks after the corresponding block, or, if the block which is X+Y blocks after the corresponding block is a bad block, to a next good block. The mapping technique can be used for a sequence of blocks in a trimmed die, where a bad block register stores physical block addresses of the trimmed away blocks.

公开(公告)号：US20210117086A1

公开(公告)日：2021-04-22

申请号：US16659353

申请日：2019-10-21

Applicant: SanDisk Technologies LLC

Inventor： Dat Tran ,  Loc Tu ,  Kirubakaran Periyannan

IPC: G06F3/06

Abstract: Consecutive logical block addresses (LBAs) are mapped to consecutive good blocks in a sequence of blocks in a memory device. For each bad block, a mapping process substitutes a next available good block. For a selected LBA, the mapping process determines a number X>1 of bad blocks before, and including, a corresponding block in the sequence, a number Y of bad blocks in the X blocks after the corresponding block in the sequence, and maps the LBA to a block which is X+Y blocks after the corresponding block, or, if the block which is X+Y blocks after the corresponding block is a bad block, to a next good block. The mapping technique can be used for a sequence of blocks in a trimmed die, where a bad block register stores physical block addresses of the trimmed away blocks.

公开(公告)号：US10908210B2

公开(公告)日：2021-02-02

申请号：US16399786

申请日：2019-04-30

Applicant: SanDisk Technologies LLC

Inventor： Kirubakaran Periyannan ,  Naresh Battula ,  Chang Siau

IPC: H01L23/52 ,  H01L23/58 ,  G01R31/28 ,  G11C16/34 ,  H01L23/528 ,  H01L23/00

Abstract: Systems and methods for die crack detection are disclosed. In one exemplary embodiment, a die includes a first conductive segment, an intermediate conductive segment, and a second conductive segment. The crack detection ring substantially surrounds the die according to a serpentine path having a plurality of legs, wherein each leg intersects the first conductive segment at a first intersection, an intermediate conductive segment at an intermediate intersection and a second conductive segment at a second intersection, wherein the intermediate intersection is horizontally offset from at least the first intersection and the second intersection.

公开(公告)号：US10290354B1

公开(公告)日：2019-05-14

申请号：US15799666

申请日：2017-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Avinash Rajagiri ,  Shantanu Gupta ,  Jagdish Sabde ,  Ashish Ghai ,  Deepak Bharadwaj ,  Sukhminder Singh Lobana ,  Shrikar Bhagath

IPC: G11C5/06 ,  G11C16/10 ,  H01L27/11573 ,  H01L27/11529 ,  G11C16/04

Abstract: A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.