公开(公告)号：US20190187553A1

公开(公告)日：2019-06-20

申请号：US15845456

申请日：2017-12-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel J. Linnen ,  Jianhua Zhu ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Avinash Rajagiri ,  Shantanu Gupta ,  Jagdish Sabde ,  Ashish Ghai ,  Deepak Bharadwaj

IPC: G03F1/50

CPC classification number: G03F1/50

Abstract: An apparatus is provided that includes a reticle including a die, the reticle configured to increase a number of partial die that can be successfully used as partially operable die.

公开(公告)号：US11947890B2

公开(公告)日：2024-04-02

申请号：US16870070

申请日：2020-05-08

Applicant: SanDisk Technologies LLC

Inventor： Cheng-Chung Chu ,  Janet George ,  Daniel J. Linnen ,  Ashish Ghai

IPC: G06F30/398 ,  G06F119/22 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  H01L21/66

CPC classification number: G06F30/398 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  H01L22/12 ,  G06F2119/22

Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

公开(公告)号：US10776277B2

公开(公告)日：2020-09-15

申请号：US15799643

申请日：2017-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Avinash Rajagiri ,  Shantanu Gupta ,  Jagdish Sabde ,  Ashish Ghai ,  Deepak Bharadwaj

IPC: G06F12/10 ,  G06F3/06 ,  G11C16/04 ,  G11C13/00 ,  G11C11/16 ,  G11C16/08 ,  G11C5/02 ,  G11C16/10 ,  G11C8/06 ,  G11C7/10

Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

公开(公告)号：US20240202425A1

公开(公告)日：2024-06-20

申请号：US18586736

申请日：2024-02-26

Applicant: SanDisk Technologies LLC

Inventor： Cheng-Chung Chu ,  Janet George ,  Daniel J. Linnen ,  Ashish Ghai

IPC: G06F30/398 ,  G06F119/22 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  H01L21/66

CPC classification number: G06F30/398 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  H01L22/12 ,  G06F2119/22

Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

公开(公告)号：US11003551B2

公开(公告)日：2021-05-11

申请号：US16361212

申请日：2019-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Ashish Ghai ,  Khanfer Kukkady

IPC: G06F11/00 ,  G06F11/14 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  G11C16/34

Abstract: A non-volatile storage apparatus receives first data from an entity external to the non-volatile storage apparatus, combines the first data with other data being stored in the non-volatile storage apparatus to create combined data, performs a programming process to program the first data into a first location, determines that the programming process failed, intentionally corrupts the first data programmed into the first location, recovers the first data from the combined data, and reprograms the recovered first into a second location.

公开(公告)号：US10290354B1

公开(公告)日：2019-05-14

申请号：US15799666

申请日：2017-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Avinash Rajagiri ,  Shantanu Gupta ,  Jagdish Sabde ,  Ashish Ghai ,  Deepak Bharadwaj ,  Sukhminder Singh Lobana ,  Shrikar Bhagath

IPC: G11C5/06 ,  G11C16/10 ,  H01L27/11573 ,  H01L27/11529 ,  G11C16/04

Abstract: A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.

公开(公告)号：US20190006021A1

公开(公告)日：2019-01-03

申请号：US15637933

申请日：2017-06-29

Applicant: SanDisk Technologies LLC

Inventor： Ashish Ghai ,  Lakshmi Kalpana Vakati ,  Ekamdeep Singh ,  Gopinath Balakrishnan

IPC: G11C29/04 ,  G11C29/02 ,  G11C16/16 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56

Abstract: A leakage current detection circuit is configured to perform an inter-block leakage current detection process to detect for leakage current between a select gate bias line associated with a first block and one or more word lines associated with a second block. During a time period, a first switching circuit may bias the select gate bias line of the first block with a first leakage detection voltage, and a second switching circuit may bias the word lines of the second block with a second leakage detection voltage. During this time period, a current sensing circuit may sense for leakage current in a global select gate bias line.

公开(公告)号：US10886002B1

公开(公告)日：2021-01-05

申请号：US16440212

申请日：2019-06-13

Applicant: SanDisk Technologies LLC

Inventor： Daniel Linnen ,  Avinash Rajagiri ,  Yuvaraj Krishnamoorthy ,  Srikar Peesari ,  Ashish Ghai ,  Dongxiang Liao

IPC: G11C29/38 ,  G06F13/16 ,  G11C16/04 ,  G11C16/14 ,  G11C29/44

Abstract: A method for detecting defects in a memory system includes receiving a command to perform a standard erase operation on at least one memory cell of the memory system. The method also includes performing a first defect detection operation on the at least one memory cell. The method also includes setting, in response to the first defect detection operation detecting a defect, a defect status indicator. The method also includes performing the standard erase operation on the at least one memory cell. The method also includes performing a second defect detection operation on the at least one memory cell. The method also includes setting, in response to the second defect detection operation detecting a defect, the defect status indicator.

公开(公告)号：US20190129861A1

公开(公告)日：2019-05-02

申请号：US15799643

申请日：2017-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Avinash Rajagiri ,  Shantanu Gupta ,  Jagdish Sabde ,  Ashish Ghai ,  Deepak Bharadwaj

IPC: G06F12/10 ,  G06F3/06 ,  G11C16/04 ,  G11C13/00 ,  G11C11/16

CPC classification number: G06F12/10 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0679 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/657 ,  G11C5/02 ,  G11C7/1039 ,  G11C8/06 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0069 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C2207/107

Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

公开(公告)号：US20180061505A1

公开(公告)日：2018-03-01

申请号：US15246309

申请日：2016-08-24

Applicant: SanDisk Technologies LLC

Inventor： Ashish Ghai ,  Lakshmi Kalpana Vakati ,  Ekamdeep Singh ,  Chang Siau ,  Gopinath Balakrishnan ,  Kapil Verma

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/16 ,  G11C16/08 ,  H01L27/115 ,  H01L27/24

CPC classification number: G11C16/3495 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/2481

Abstract: Technology is described herein for detecting a leakage current between a block select line and a conductive region that exists in multiple blocks of memory cells in a plane. The conductive region may be shared by at least one memory cell in multiple blocks. One example of the conductive region is a common source line that includes one or more local source lines and one or more global source lines. If the leakage current were to become high enough, the electrical short between the conductive region and the block select line could cause a plane level failure. If the leakage current is less than an amount that would cause a plane failure, but that indicates that the non-volatile memory device is susceptible to a plane failure, data may be moved out of the plane before the plane failure occurs. Thus, data loss may be prevented.