公开(公告)号：US20220108740A1

公开(公告)日：2022-04-07

申请号：US17061636

申请日：2020-10-02

Applicant: SanDisk Technologies LLC

Inventor： Ward Parkinson ,  James O'Toole ,  Nathan Franklin ,  Thomas Trent

IPC: G11C11/16

Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may turned on while the pMOSFET is turned off. The nMOSFET provides a higher resistance in place of the decreased resistance of the pMOSFET to amplify a signal at a sense circuit to allow accurate sensing of the voltage across the memory cell.

公开(公告)号：US12300296B2

公开(公告)日：2025-05-13

申请号：US18618754

申请日：2024-03-27

Applicant: SanDisk Technologies LLC

Inventor： Michael Nicolas Albert Tran ,  Michael K. Grobis ,  Ward Parkinson ,  Nathan Franklin

IPC: G11C11/16 ,  G06F11/10

Abstract: Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.

公开(公告)号：US12148459B2

公开(公告)日：2024-11-19

申请号：US17677666

申请日：2022-02-22

Applicant: SanDisk Technologies LLC

Inventor： Ward Parkinson ,  James O'Toole ,  Thomas Trent ,  Nathan Franklin ,  Michael Grobis ,  James W. Reiner ,  Hans Jurgen Richter ,  Michael Nicolas Albert Tran

IPC: G11C11/16 ,  G11C13/00 ,  H10N50/10 ,  H10N70/20

Abstract: Technology for read in a cross-point memory array. Drive transistors pass read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to a drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector.

公开(公告)号：US20230100600A1

公开(公告)日：2023-03-30

申请号：US17485129

申请日：2021-09-24

Applicant: SanDisk Technologies LLC

Inventor： Michael Nicolas Albert Tran ,  Ward Parkinson ,  Michael Grobis ,  Nathan Franklin ,  Raj Ramanujan

IPC: G11C11/16 ,  H01L27/22 ,  G06F11/10

Abstract: Technology for reading reversible resistivity cells in a memory array when using a current-force read is disclosed. The memory cells are first read using a current-force referenced read. If the current-force referenced read is successful, then results of the current-force referenced read are returned. If the current-force referenced read is unsuccessful, then a current-force self-referenced read (SRR) is performed and results of the current-force SRR are returned. The current-force referenced read provides a very fast read of the memory cells and can be successful in most cases. The current-force SRR provides a more accurate read in the event that the current-force referenced read is not successful. Moreover, the current-force referenced read may use less power than the current-force SRR. In an aspect this mixed current-force read is used for MRAM cells, which are especially challenging to read.

公开(公告)号：US20220335998A1

公开(公告)日：2022-10-20

申请号：US17846678

申请日：2022-06-22

Applicant: SanDisk Technologies LLC

Inventor： Michael Nicolas Albert Tran ,  Ward Parkinson ,  Michael Grobis ,  Nathan Franklin

IPC: G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22

Abstract: Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.

公开(公告)号：US20220157376A1

公开(公告)日：2022-05-19

申请号：US17099030

申请日：2020-11-16

Applicant: SanDisk Technologies LLC

Inventor： Nathan Franklin ,  Ward Parkinson ,  Michael Grobis ,  James O'Toole

IPC: G11C11/56 ,  H01L25/065 ,  H01L23/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16

Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

公开(公告)号：US10885991B2

公开(公告)日：2021-01-05

申请号：US16359846

申请日：2019-03-20

Applicant: SanDisk Technologies LLC

Inventor： Ward Parkinson ,  Martin Hassner ,  Nathan Franklin ,  Christopher Petti

IPC: G11C16/34 ,  G06F3/06 ,  G06F11/08 ,  G06F12/02

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for data rewrite operations. A non-volatile memory device comprises a non-volatile memory medium. A non-volatile memory device is configured to determine an error metric for a non-volatile memory medium in response to a read request for the non-volatile memory medium. A non-volatile memory device is configured to receive a refresh command from a controller over a bus. A non-volatile memory device is configured to rewrite data from a non-volatile memory medium during a predefined time period after receiving a refresh command in response to an error metric satisfying an error threshold.

公开(公告)号：US20240265958A1

公开(公告)日：2024-08-08

申请号：US18618754

申请日：2024-03-27

Applicant: SanDisk Technologies LLC

Inventor： Michael Nicolas Albert Tran ,  Michael K. Grobis ,  Ward Parkinson ,  Nathan Franklin

IPC: G11C11/16 ,  G06F11/10

CPC classification number: G11C11/1659 ,  G06F11/1044 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675

Abstract: Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.

公开(公告)号：US11972822B2

公开(公告)日：2024-04-30

申请号：US17552143

申请日：2021-12-15

Applicant: SanDisk Technologies LLC

Inventor： Martin Hassner ,  Michael Nicolas Albert Tran ,  Ward Parkinson ,  Michael Grobis ,  Nathan Franklin ,  Raj Ramanujan

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/4401 ,  G11C2029/1802

Abstract: Technology is disclosed for a fast ECC engine for a mixed read of MRAM cells. A codeword read from MRAM cells using a referenced read is decoded using a first ECC mode. If decoding passes, results are provided to a host. If decoding fails, a self-referenced read (SRR) is performed. The data read using the SRR is decoded with a second ECC mode that is capable of correcting a greater number of bits than the first ECC mode. The second ECC mode may have a higher mis-correction rate than the first ECC mode (for a given raw bit error rate (RBER)). However, the RBER may be lower when using the second ECC mode. Therefore, the first and second ECC modes may result in about the same probability of an undetectable error (or mis-correction).

公开(公告)号：US11854592B2

公开(公告)日：2023-12-26

申请号：US17828905

申请日：2022-05-31

Applicant: SanDisk Technologies LLC

Inventor： Ward Parkinson ,  James O'Toole ,  Nathan Franklin ,  Thomas Trent

IPC: G11C11/16 ,  H10N50/80

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H10N50/80

Abstract: A control circuit is configured to connect to a cross-point memory array in which each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET in a conductive state while the nMOSFET is in a non-conductive state. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be in a conductive state.