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公开(公告)号：US08384447B2
公开(公告)日：2013-02-26
申请号：US13584519
申请日：2012-08-13
Applicant: Sin Hyun Jin , Sang Jin Byeon
Inventor： Sin Hyun Jin , Sang Jin Byeon
IPC: H03L7/00
CPC classification number: H03K17/22 , H01L25/065 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.
Abstract translation: 半导体装置包括被配置为产生上电信号的上电信号生成部，被配置为驱动和输出上电信号的驱动器，以及主电路块，被配置为响应于来自所述上电信号的输出执行预定功能 驱动器，其中所述加电信号产生部分和所述驱动器的输入端子通过可断开元件连接。
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公开(公告)号：US08344783B2
公开(公告)日：2013-01-01
申请号：US12970623
申请日：2010-12-16
Applicant: Jae Bum Ko , Jong Chern Lee , Sang Jin Byeon
Inventor： Jae Bum Ko , Jong Chern Lee , Sang Jin Byeon
IPC: H03H11/26
CPC classification number: H03K5/1506 , H03K5/05
Abstract: A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal.
Abstract translation: 延迟电路包括：延迟单元，被配置为接收时钟信号，按预定时间间隔顺序地延迟输入信号，并输出多个第一延迟信号; 以及选择单元，被配置为基于一个或多个选择信号来选择所述多个第一延迟信号中的一个，并输出第二延迟信号。
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公开(公告)号：US08274316B2
公开(公告)日：2012-09-25
申请号：US12651018
申请日：2009-12-31
Applicant: Sin Hyun Jin , Sang Jin Byeon
Inventor： Sin Hyun Jin , Sang Jin Byeon
IPC: H03L7/00
CPC classification number: H03K17/22 , H01L25/065 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.
Abstract translation: 半导体装置包括被配置为产生上电信号的上电信号生成部，被配置为驱动和输出上电信号的驱动器，以及主电路块，被配置为响应于来自所述上电信号的输出执行预定功能 驱动器，其中所述加电信号产生部分和所述驱动器的输入端子通过可断开元件连接。
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公开(公告)号：US08179737B2
公开(公告)日：2012-05-15
申请号：US12431981
申请日：2009-04-29
Applicant: Sang Jin Byeon
Inventor： Sang Jin Byeon
IPC: G11C5/04
CPC classification number: G11C5/147 , G11C7/1045
Abstract: A semiconductor memory apparatus includes an internal circuit configured to be driven by current flowing between first and second voltage nodes, and a current control unit configured to control an amount of the current in response to an operational-speed information signal.
Abstract translation: 一种半导体存储装置，包括被配置为由在第一和第二电压节点之间流动的电流驱动的内部电路，以及被配置为响应于操作速度信息信号来控制电流量的电流控制单元。
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公开(公告)号：US20110241763A1
公开(公告)日：2011-10-06
申请号：US12840212
申请日：2010-07-20
Applicant: Jae Bum Ko , Sang Jin Byeon
Inventor： Jae Bum Ko , Sang Jin Byeon
IPC: H03K19/003
CPC classification number: G11C8/12
Abstract: A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating codes which have different code values or at least two of which have the same code value, in response to a plurality of chip fuse signals; and an individual chip activation block configured to compare the plurality of individual chip designating codes with chip selection address in response to the plurality of chip fuse signals, and enable one of a plurality of individual chip activation signals based on a result of the comparison.
Abstract translation: 半导体装置包括单独的芯片指定代码设置块，其被配置为响应于多个芯片熔丝信号而生成具有不同代码值的多个独立芯片指定代码或其中至少两个具有相同代码值的单独芯片指定代码; 以及单个芯片激活块，其被配置为响应于所述多个芯片熔丝信号来比较所述多个独立芯片指定代码与芯片选择地址，并且基于所述比较的结果来启用多个单独芯片激活信号中的一个。
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Patent Agency Ranking
公开(公告)号：US20110210780A1
公开(公告)日：2011-09-01
申请号：US12839333
申请日：2010-07-19
Applicant: Jae Bum Ko , Sang Jin Byeon
Inventor： Jae Bum Ko , Sang Jin Byeon
IPC: H03L5/00
CPC classification number: G06F1/10
Abstract: A semiconductor integrated circuit includes: a plurality of chips configured to receive an external voltage. Each one of the chips detects a signal delay characteristic of the one of the chips to generate an internal voltage having a level corresponding to the signal delay characteristic.
Abstract translation: 半导体集成电路包括：被配置为接收外部电压的多个芯片。 每个芯片检测到芯片之一的信号延迟特性，以产生具有与信号延迟特性对应的电平的内部电压。
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公开(公告)号：US20080061856A1
公开(公告)日：2008-03-13
申请号：US11819424
申请日：2007-06-27
Applicant: Sang Jin Byeon
Inventor： Sang Jin Byeon
CPC classification number: G05F1/465
Abstract: An internal voltage generator of a semiconductor integrated circuit includes a first driver that outputs an internal voltage by using an internal reference voltage during an active operation in accordance with a detection signal generated by using an external voltage and an active enable signal activated during an activation mode, and a second driver that outputs an internal voltage by using the internal reference voltage during the active operation in accordance with the active enable signal.
Abstract translation: 半导体集成电路的内部电压发生器包括：第一驱动器，其根据通过使用外部电压产生的检测信号和在激活模式下激活的有效使能信号，在有效操作期间使用内部参考电压来输出内部电压 以及第二驱动器，其根据有效使能信号在有效操作期间通过使用内部基准电压输出内部电压。
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公开(公告)号：US08400210B2
公开(公告)日：2013-03-19
申请号：US12840212
申请日：2010-07-20
Applicant: Jae Bum Ko , Sang Jin Byeon
Inventor： Jae Bum Ko , Sang Jin Byeon
IPC: H03K19/003
CPC classification number: G11C8/12
Abstract: A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating codes which have different code values or at least two of which have the same code value, in response to a plurality of chip fuse signals; and an individual chip activation block configured to compare the plurality of individual chip designating codes with chip selection address in response to the plurality of chip fuse signals, and enable one of a plurality of individual chip activation signals based on a result of the comparison.
Abstract translation: 半导体装置包括单独的芯片指定代码设置块，其被配置为响应于多个芯片熔丝信号而生成具有不同代码值的多个独立芯片指定代码或其中至少两个具有相同代码值的单独芯片指定代码; 以及单个芯片激活块，其被配置为响应于所述多个芯片熔丝信号来比较所述多个独立芯片指定代码与芯片选择地址，并且基于所述比较的结果来启用多个单独芯片激活信号中的一个。
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公开(公告)号：US08300496B2
公开(公告)日：2012-10-30
申请号：US12948874
申请日：2010-11-18
Applicant: Tae Sik Yun , Hyung Dong Lee , Jun Gi Choi , Sang Jin Byeon , Sang Hoon Shin
Inventor： Tae Sik Yun , Hyung Dong Lee , Jun Gi Choi , Sang Jin Byeon , Sang Hoon Shin
CPC classification number: G11C7/22 , G11C7/222 , G11C29/006 , G11C29/023
Abstract: A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.
Abstract translation: 一种半导体存储装置，包括：时钟控制单元，被配置为当使能信号被激活时接收第一时钟，并产生具有与第一时钟相对于目标时钟周期更长的周期的第二时钟; DLL输入时钟生成单元，被配置为根据DLL选择信号将第一时钟和第二时钟中的一个作为DLL输入时钟输出; 以及地址/命令输入时钟生成单元，被配置为根据使能信号将第一时钟和第二时钟中的一个作为AC输入时钟输出。
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公开(公告)号：US20120119357A1
公开(公告)日：2012-05-17
申请号：US13166118
申请日：2011-06-22
Applicant: Sang Jin Byeon , Tae Kyun Kim
Inventor： Sang Jin Byeon , Tae Kyun Kim
IPC: H01L23/48 , H01L23/498
CPC classification number: H01L25/0657 , G11C5/02 , G11C5/06 , H01L24/16 , H01L2224/0401 , H01L2224/05553 , H01L2224/05569 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49113 , H01L2225/06544 , H01L2924/00013 , H01L2924/00014 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
Abstract: A semiconductor apparatus having stacked first and second chips includes a first through line of the first chip configured to receive a first coding signal and be electrically connected to a first through line of the second chip; a second through line of the first chip configured to receive a second coding signal; and a second through line of the second chip configured to be electrically connected to the first through line of the first chip and receive the first coding signal.
Abstract translation: 具有堆叠的第一和第二芯片的半导体装置包括：第一芯片的第一直线，被配置为接收第一编码信号并与第二芯片的第一直线电连接; 所述第一芯片的第二直线被配置为接收第二编码信号; 以及第二芯片的第二直线，被配置为电连接到第一芯片的第一直线并接收第一编码信号。
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