公开(公告)号：US08227788B2

公开(公告)日：2012-07-24

申请号：US12863535

申请日：2009-11-18

申请人： Takumi Mikawa ,  Kiyotaka Tsuji ,  Takashi Okada

发明人： Takumi Mikawa ,  Kiyotaka Tsuji ,  Takashi Okada

IPC分类号： H01L21/00

CPC分类号： G11C13/003 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/72 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675 ,  H01L45/1683

摘要： A nonvolatile memory element comprises a resistance variable element 105 configured to reversibly change between a low-resistance state and a high-resistance state in response to electric signals with different polarities which are applied thereto; and a current controlling element 112 configured such that when a current flowing when a voltage whose absolute value is a first value as a desired value which is larger than 0 and smaller than a predetermined voltage value and whose polarity is a first polarity is applied is a first current and a current flowing when a voltage whose absolute value is the first value and whose polarity is a second polarity different from the first polarity is applied is a second current, the first current is higher than the second current, and the resistance variable element is connected in series with the current controlling element such that a polarity of a voltage applied to the current controlling element when the resistance variable element is changed from the low-resistance state to the high-resistance state is the first polarity.

摘要翻译： 非易失性存储元件包括电阻可变元件105，其被配置为响应于施加到其上的具有不同极性的电信号在低电阻状态和高电阻状态之间可逆地变化; 以及电流控制元件112，被配置为当施加绝对值为第一值的电压作为大于0且小于预定电压值且极性为第一极性的期望值的电流流过的电流控制元件112为 当施加绝对值为第一值且极性为与第一极性不同的第二极性的电压时的第一电流和电流是第二电流，第一电流高于第二电流，并且电阻可变元件 与电流控制元件串联连接，使得当电阻可变元件从低电阻状态改变为高电阻状态时施加到电流控制元件的电压的极性是第一极性。

公开(公告)号：US20120181500A1

公开(公告)日：2012-07-19

申请号：US13498541

申请日：2011-07-07

申请人： Kiyotaka Tsuji ,  Takumi Mikawa ,  Kenji Tominaga

发明人： Kiyotaka Tsuji ,  Takumi Mikawa ,  Kenji Tominaga

IPC分类号： H01L47/00 ,  H01L21/02

CPC分类号： H01L27/2463 ,  H01L21/76879 ,  H01L45/04 ,  H01L45/146 ,  H01L45/1683

摘要： A non-volatile semiconductor memory device comprises a plurality of memory cell holes (101) formed through an interlayer insulating layer (80) at respective cross-points of a plurality of first wires (10) of a stripe shape and a plurality of second wires (20) of a stripe shape when viewed from above such that the memory cell holes (101) expose upper surfaces of the plurality of first wires, respectively, a plurality of dummy holes (111) formed on the plurality of first wires in the interlayer insulating layer such that the dummy holes reach the upper surfaces of the plurality of first wires, respectively, and stacked-layer structures formed inside the memory cell holes and inside the dummy holes, respectively, each of the stacked-layer structures including a first electrode (30) and a variable resistance layer (40); an area of a portion of the first wire which is exposed in a lower opening of one of the dummy holes being greater than an area of a portion of the first wire which is exposed in a lower opening of one of the memory cell holes; and one or more of the dummy holes being formed on each of the first wires.

摘要翻译： 一种非易失性半导体存储器件包括：多条存储单元孔（101），其形成在层状绝缘层（80）的多个第一布线（10）的条状形状的各个交叉点处，多个第二布线 （101）分别暴露在所述多个第一布线的上表面的多个虚设孔（111），所述多个第一布线形成在所述中间层 绝缘层，使得所述虚拟孔分别到达所述多个第一布线的上表面，分别形成在所述存储单元孔内部和所述虚拟孔内部的堆叠层结构，所述层叠层结构中的每一个包括第一电极 （30）和可变电阻层（40）; 在一个虚拟孔的下部开口中露出的第一线的一部分的面积大于暴露在一个存储单元孔的下部开口中的第一线的一部分的面积; 并且在每个第一导线上形成一个或多个虚拟孔。

公开(公告)号：US08350245B2

公开(公告)日：2013-01-08

申请号：US13133809

申请日：2009-12-08

申请人： Kiyotaka Tsuji

发明人： Kiyotaka Tsuji

IPC分类号： H01L29/02

CPC分类号： H01L27/101 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

摘要： To provide a variable resistance element capable of preventing the interface resistance, in a side of the variable resistance element in which resistance change is not allowed, from changing to high resistance due to applied voltage. The variable resistance element is configured by providing a variable resistance film (265) between a first electrode (280) and a second electrode (250), the oxygen concentration within the film of the variable resistance film (265) is high at the side of an interface with the second electrode (250) (high-concentration variable resistance layer (260)) and low at the side of an interface with the first electrode (280) (low-concentration variable resistance layer (270)), and the junction surface area between the low-concentration variable resistance layer (270) and the first electrode (280) is larger than the interface surface area between the high-concentration variable resistance layer (260) and the second electrode (250).

摘要翻译： 为了提供一种可变电阻元件，能够防止在不允许电阻变化的可变电阻元件侧的界面电阻由于施加的电压而变为高电阻。 可变电阻元件通过在第一电极（280）和第二电极（250）之间设置可变电阻膜（265）而构成，可变电阻膜（265）的膜内的氧浓度在 与第二电极（250）（高浓度可变电阻层（260））的界面和与第一电极（280）的界面侧的低（低浓度可变电阻层（270））的界面， 低浓度可变电阻层（270）和第一电极（280）之间的表面积大于高浓度可变电阻层（260）和第二电极（250）之间的界面面积。

公开(公告)号：US20110074539A1

公开(公告)日：2011-03-31

申请号：US12994916

申请日：2010-04-14

申请人： Kiyotaka Tsuji

发明人： Kiyotaka Tsuji

IPC分类号： H01C7/10 ,  H01C17/00

CPC分类号： H01L45/1246 ,  H01L27/101 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1683 ,  Y10T29/49082

摘要： A variable resistance element capable of increasing stability of a resistance changing operation and reducing a current necessary for changing, to a low resistance state for the first time, the variable resistance element in an initial state immediately after manufacture. The variable resistance element includes: a first electrode (101); a memory cell hole (150) formed above the first electrode (101); a first variable resistance layer (201) covering a bottom of the memory cell hole (150) and an upper surface of the first electrode (101); a second variable resistance layer (202) formed on the first variable resistance layer (201); and a second electrode (102) formed on the memory cell hole (150), in which a thickness of the first variable resistance layer (201) at the bottom of the memory cell hole (150) gradually decreases toward an edge area of the memory cell hole (150) and has a local minimum value around the edge area of the memory cell hole (150). Furthermore, an oxygen concentration in the first variable resistance layer (201) is higher than an oxygen concentration in the second variable resistance layer (202).

摘要翻译： 一种可变电阻元件，其能够增加电阻变化操作的稳定性，并且减少在制造后立即将初始状态中的可变电阻元件首次变为低电阻状态所需的电流。 可变电阻元件包括：第一电极（101）; 形成在所述第一电极（101）上方的存储单元孔（150）; 覆盖存储单元孔（150）底部的第一可变电阻层（201）和第一电极（101）的上表面; 形成在第一可变电阻层（201）上的第二可变电阻层（202）; 以及形成在存储单元孔（150）上的第二电极（102），其中存储单元孔（150）底部的第一可变电阻层（201）的厚度朝向存储器的边缘区域逐渐减小 电池孔（150），并且在存储单元孔（150）的边缘区域周围具有局部最小值。 此外，第一可变电阻层（201）中的氧浓度高于第二可变电阻层（202）中的氧浓度。

公开(公告)号：US20060056250A1

公开(公告)日：2006-03-16

申请号：US10512545

申请日：2003-04-21

申请人： Sadahiko Miura ,  Tadahiko Sugibayashi ,  Hideaki Numata ,  Kiyotaka Tsuji

发明人： Sadahiko Miura ,  Tadahiko Sugibayashi ,  Hideaki Numata ,  Kiyotaka Tsuji

IPC分类号： G11C7/00

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/16

摘要： A technology for eliminating the defects in a tunnel insulation film of magnetic tunnel junction and for suppressing generation of a defective bit in an MRAM using magnetic tunnel junction in a memory. The magnetic memory includes a substrate, an interlayer insulation film covering the upper surface side of the substrate, memory cells, and plugs penetrating the interlayer insulation film. The memory cell includes a first magnetic layer formed on the upper surface side of the interlayer insulation film, a tunnel insulation layer formed on the first magnetic layer, and a second magnetic layer formed on the tunnel insulation layer. The plug is connected electrically with the first magnetic layer. The tunnel current passing part of the tunnel insulation layer located between the first and second magnetic layers is arranged, at least partially, so as not to overlap the plug in the direction perpendicular to the surface of the substrate.

摘要翻译： 一种用于消除磁隧道结隧道绝缘膜中的缺陷并用于抑制在存储器中使用磁性隧道结的MRAM中的有缺陷位的产生的技术。 磁性存储器包括基板，覆盖基板的上表面侧的层间绝缘膜，存储单元和穿透层间绝缘膜的插塞。 存储单元包括形成在层间绝缘膜的上表面侧的第一磁性层，形成在第一磁性层上的隧道绝缘层和形成在隧道绝缘层上的第二磁性层。 插头与第一磁性层电连接。 位于第一和第二磁性层之间的隧道绝缘层的隧道电流通过部分被布置成至少部分地不与垂直于衬底的表面的方向上的插塞重叠。

公开(公告)号：US20130148407A1

公开(公告)日：2013-06-13

申请号：US13700346

申请日：2012-06-18

申请人： Kiyotaka Tsuji ,  Kazuhiko Shimakawa

发明人： Kiyotaka Tsuji ,  Kazuhiko Shimakawa

IPC分类号： G11C13/00

CPC分类号： G11C13/004 ,  G11C11/1673 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C2013/0054 ,  G11C2213/77

摘要： A nonvolatile semiconductor memory device includes: word lines; bit lines formed so as to three-dimensionally cross the word lines; and a cross-point cell array including cells each provided at a corresponding one of three-dimensional cross-points of the word lines and the bit lines. The cells include: a memory cell including a memory element that operates as a memory by reversibly changing in resistance value between at least two states based on an electrical signal; and an offset detection cell having a constant resistance value that is higher than the resistance value of the memory element in a high resistance state which is a state of the memory element when operating as the memory.

摘要翻译： 非易失性半导体存储器件包括：字线; 形成为三维地跨越字线的位线; 以及包括各自提供在字线和位线的三维交叉点中的相应一个的单元的交叉点单元阵列。 单元包括：存储单元，其包括通过基于电信号在至少两个状态之间可逆地改变电阻值而作为存储器操作的存储元件; 以及偏移检测单元，其具有比作为存储器操作时作为存储元件的状态的高电阻状态下的存储元件的电阻值高的恒定电阻值。

公开(公告)号：US20120193600A1

公开(公告)日：2012-08-02

申请号：US13499961

申请日：2011-07-01

申请人： Atsushi Himeno ,  Kiyotaka Tsuji

发明人： Atsushi Himeno ,  Kiyotaka Tsuji

IPC分类号： H01L47/00 ,  H01L21/02

CPC分类号： H01L27/2463 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/1625 ,  H01L45/1683

摘要： A variable resistance nonvolatile memory element (10) is formed from a first electrode (101) comprising a material including a metal as a main component, a variable resistance layer (102) having a reversibly changing resistance value in response to applied predetermined electric pulses having different polarities, a semiconductor layer (103) comprising a material including a nitrogen-deficient silicon nitride as a main component, and a second electrode (104). The variable resistance layer (102) includes a first variable resistance layer (102a) adjacent to the first electrode (101) and a second variable resistance layer (102b), both comprising a material including an oxygen-deficient transition metal oxide as a main component. The first variable resistance layer (102a) has a higher oxygen content atomic percentage than the second variable resistance layer (102b). A stacked structure of the variable resistance layer (102), the semiconductor layer (103), and the second electrode (104) functions as a bidirectional diode element (106).

摘要翻译： 可变电阻非易失性存储元件（10）由包括以金属为主要成分的材料的第一电极（101）形成，可变电阻层（102）响应于所施加的预定电脉冲具有可逆变化的电阻值， 不同极性的半导体层（103）和第二电极（104），包括氮缺乏氮化物作为主要成分的材料。 可变电阻层（102）包括与第一电极（101）相邻的第一可变电阻层（102a）和第二可变电阻层（102b），二者包括以氧缺乏的过渡金属氧化物为主要成分的材料 。 第一可变电阻层（102a）具有比第二可变电阻层（102b）更高的氧含量原子百分比。 可变电阻层（102），半导体层（103）和第二电极（104）的堆叠结构用作双向二极管元件（106）。

公开(公告)号：US20110240942A1

公开(公告)日：2011-10-06

申请号：US13133809

申请日：2009-12-08

申请人： Kiyotaka Tsuji

发明人： Kiyotaka Tsuji

IPC分类号： H01L45/00

CPC分类号： H01L27/101 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

摘要： To provide a variable resistance element capable of preventing the interface resistance, in a side of the variable resistance element in which resistance change is not allowed, from changing to high resistance due to applied voltage. The variable resistance element is configured by providing a variable resistance film (265) between a first electrode (280) and a second electrode (250), the oxygen concentration within the film of the variable resistance film (265) is high at the side of an interface with the second electrode (250) (high-concentration variable resistance layer (260)) and low at the side of an interface with the first electrode (280) (low-concentration variable resistance layer (270)), and the junction surface area between the low-concentration variable resistance layer (270) and the first electrode (280) is larger than the interface surface area between the high-concentration variable resistance layer (260) and the second electrode (250).

摘要翻译： 为了提供一种可变电阻元件，能够防止在不允许电阻变化的可变电阻元件侧的界面电阻由于施加的电压而变为高电阻。 可变电阻元件通过在第一电极（280）和第二电极（250）之间设置可变电阻膜（265）而构成，可变电阻膜（265）的膜内的氧浓度在 与第二电极（250）（高浓度可变电阻层（260））的界面和与第一电极（280）的界面侧的低（低浓度可变电阻层（270））的界面， 低浓度可变电阻层（270）和第一电极（280）之间的表面积大于高浓度可变电阻层（260）和第二电极（250）之间的界面面积。

公开(公告)号：US07628903B1

公开(公告)日：2009-12-08

申请号：US09563479

申请日：2000-05-02

申请人： Kiyotaka Tsuji ,  Tetsuji Nishikawa ,  Takao Takeuchi ,  Keigo Obata ,  Hidemi Nawafune

发明人： Kiyotaka Tsuji ,  Tetsuji Nishikawa ,  Takao Takeuchi ,  Keigo Obata ,  Hidemi Nawafune

IPC分类号： C25D3/46 ,  C23C18/31

CPC分类号： C25D3/46 ,  C25D3/64

摘要： A silver and silver alloy plating bath, includes (A) a soluble salt, having a silver salt or a mixture of a silver salt and a salt of a metal such as tin, bismuth, indium, lead, and the like; and (B) a particular aliphatic sulfide compound, such as thiobis(diethyleneglycol), dithiobis(triglycerol), 3,3′-thiodipropanol, thiodiglycerin, 3,6-dithiooctane-1,8-diol, and the like, which contain at least one or more of an ether oxygen atom, a 1-hydroxypropyl group, a hydroxypropylene group, or two or more of a sulfide bond in the molecule, and not containing a basic nitrogen atom. Compared to baths containing aliphatic monosulfide compounds, such as thiodiglycol or beta-thiodiglycol, which do not contain an ether oxygen atom, 1-hydroxypropyl group, a hydroxypropylene group, or two or more of a sulfide bond in the molecule, by having these particular compounds, the plating bath of the present invention has excellent stability over extended time, excellent co-deposition of silver and various metals, and excellent appearance of the electrodeposition coating.

摘要翻译： 银和银合金电镀浴包括（A）可溶性盐，其具有银盐或银盐和金属如锡，铋，铟，铅等的盐的混合物; 和（B）特定的脂族硫醚化合物，例如硫代双（二甘醇），二硫代双（三甘油），3,3'-硫代二丙醇，硫二甘油，3,6-二硫辛烷-1,8-二醇等， 至少一个或多个醚氧原子，1-羟丙基，羟基亚丙基，或分子中的硫原子键中的两个或多个，并且不含碱性氮原子。 与分子中含有不含醚氧原子，1-羟丙基，羟基亚丙基或两个或多个硫键的脂族单硫醚化合物如硫二甘醇或β-硫二甘醇相比，具有这些特定 化合物，本发明的电镀浴在延长的时间内具有优异的稳定性，优异的银和各种金属的共沉积，以及优异的电沉积外观。

公开(公告)号：US06184778B2

公开(公告)日：2001-02-06

申请号：US09101618

申请日：1998-07-13

申请人： Kiyotaka Tsuji

发明人： Kiyotaka Tsuji

IPC分类号： G08B900

CPC分类号： H04L12/437 ,  H04L12/42

摘要： A communications network system capable of reducing the time from the occurrence of a trouble to the rebuilding of the system and a rebuilding method thereof. In a communications network system which comprises a plurality of node devices (10-1 to 10-4) distributed at a plurality of positions and transmission lines (1a, 1b) for connecting the plurality of node devices, one of the plurality of node devices is set as a master station (10-1) to operate the system, when the master station has a trouble, the individual node device makes an inquiry to the other node devices, and a node device which has confirmed that no other node device has a higher priority than itself becomes a substitute master station to take the place of the troubled master station to continue the operation of the system.

摘要翻译： 一种能够减少从故障发生到重建系统的时间的通信网络系统及其重建方法。 在包括分布在多个位置的多个节点设备（10-1至10-4）和用于连接多个节点设备的传输线（1a，1b）的通信网络系统中，多个节点设备 被设置为主站（10-1）以操作系统，当主站有故障时，单个节点设备对其他节点设备进行查询，并且确认没有其他节点设备具有的节点设备 比本身更高的优先级成为替代主站来代替困扰的主站继续运行系统。