公开(公告)号：US20230352090A1

公开(公告)日：2023-11-02

申请号：US17791326

申请日：2020-12-28

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazuki TSUDA ,  Hiromichi GODO ,  Satoru OHSHITA ,  Hitoshi KUNITAKE ,  Satoru OKAMOTO

IPC: G11C16/04 ,  H01L29/786 ,  H01L23/528 ,  H10B43/10 ,  H10B43/35 ,  H10B43/27

CPC classification number: G11C16/0483 ,  H01L29/7869 ,  H01L23/5283 ,  H10B43/10 ,  H10B43/35 ,  H10B43/27

Abstract: A highly reliable memory device is provided. The memory device includes a first conductor, a second conductor above the first conductor, a third conductor above the second conductor, a fourth conductor above the third conductor, a fifth conductor above the fourth conductor, a sixth conductor above the fifth conductor, a seventh conductor, a first insulator, a second insulator, a first semiconductor, and a second semiconductor. At least third conductor and the fourth conductor have an opening. The first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided in this order on an inner surface of the opening. The seventh conductor is provided between the first semiconductor and the second insulator in a region between the third conductor and the second insulator. The first semiconductor is electrically connected to the second conductor and the fifth conductor. The second semiconductor is electrically connected to the first conductor and the sixth conductor.

公开(公告)号：US20220375956A1

公开(公告)日：2022-11-24

申请号：US17772280

申请日：2020-11-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Satoru OHSHITA ,  Kazuki TSUDA ,  Tatsuya ONUKI

IPC: H01L27/11573 ,  H01L27/11582 ,  G11C16/08

Abstract: A memory device with a small number of wirings using a NAND flash memory having a three-dimensional structure with a large number of stacked memory cell layers is provided. A decoder is formed using an OS transistor. An OS transistor can be formed by a method such as a thin film method, whereby the decoder can be provided to be stacked above the NAND flash memory having a three-dimensional structure. This can reduce the number of wirings provided substantially perpendicular to the memory cell layers.

公开(公告)号：US20220345095A1

公开(公告)日：2022-10-27

申请号：US17619669

申请日：2020-06-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Takayuki IKEDA ,  Kiyoshi KATO ,  Yuichi YANAGISAWA ,  Shota MIZUKAMI ,  Kazuki TSUDA

IPC: H03F3/195 ,  H03F1/02 ,  H01L29/786

Abstract: A semiconductor device is provided in which power consumption is reduced and an increase in circuit area is inhibited. The semiconductor device includes a high frequency amplifier circuit, an envelope detection circuit, and a power supply circuit. The power supply circuit has a function of supplying a power supply potential to the high frequency amplifier circuit, an output of the high frequency amplifier circuit is connected to the envelope detection circuit, and an output of the envelope detection circuit is connected to the power supply circuit. The power supply circuit can reduce the power consumption by changing the power supply potential in accordance with the output of the high frequency amplifier circuit. The use of an OS transistor in the envelope detection circuit can inhibit an increase in circuit area.

公开(公告)号：US20220302312A1

公开(公告)日：2022-09-22

申请号：US17642346

申请日：2020-09-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi Kunitake ,  Yuichi YANAGISAWA ,  Shota MIZUKAMI ,  Kazuki TSUDA ,  Haruyuki BABA ,  Shunpei YAMAZAKI

IPC: H01L29/786

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a first conductor, a second conductor, a third oxide, a fourth oxide, and a second insulator over the second oxide; a third insulator over the first conductor, the second conductor, the third oxide, and the fourth oxide; a fourth insulator over the second insulator; and a third conductor over the fourth insulator. The second insulator is positioned between the first conductor and the second conductor. The third oxide is positioned between the first conductor and the second insulator. The fourth oxide is positioned between the second conductor and the second insulator. The thickness of the third oxide between the first conductor and the second insulator is greater than or equal to 3 nm and less than or equal to 8 nm. The thickness of the fourth oxide between the second conductor and the second insulator is greater than or equal to 3 nm and less than or equal to 8 nm.

公开(公告)号：US20220208794A1

公开(公告)日：2022-06-30

申请号：US17606533

申请日：2020-04-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Kazuaki OHSHIMA ,  Kazuki TSUDA ,  Tomoaki ATSUMI

IPC: H01L27/12 ,  H01L27/108 ,  H01L29/786

Abstract: A semiconductor device with a small characteristic variation due to operating temperature is provided. The semiconductor device includes an odd number of stages of inverter circuits that are circularly connected. The inverter circuit includes a first transistor and a second transistor. A gate of the first transistor is electrically connected to one of a source and a drain of the first transistor, the one of the source and the drain of the first transistor is supplied with a high power supply potential, and the other of the source and the drain of the first transistor is electrically connected to an output terminal out. A gate of the second transistor is electrically connected to an input terminal in, one of a source and a drain of the second transistor is electrically connected to the output terminal out, and the other of the source and the drain of the second transistor is supplied with a low power supply potential. The first transistor and the second transistor include an oxide semiconductor in a semiconductor layer. The first transistor and the second transistor each include a back gate.

公开(公告)号：US20250072009A1

公开(公告)日：2025-02-27

申请号：US18947085

申请日：2024-11-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Takanori MATSUZAKI ,  Tatsuya ONUKI ,  Yuki OKAMOTO ,  Hideki UOCHI ,  Satoru OKAMOTO ,  Hiromichi GODO ,  Kazuki TSUDA ,  Hitoshi KUNITAKE

IPC: H10B63/00

Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

公开(公告)号：US20240237435A1

公开(公告)日：2024-07-11

申请号：US18288495

申请日：2022-04-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuki TSUDA ,  Hidefumi RIKIMARU ,  Satoru OHSHITA ,  Hiromichi GODO ,  Yoshiyuki KUROKAWA

IPC: H10K59/131

CPC classification number: H10K59/131

Abstract: A semiconductor device with reduced circuit area is provided. The semiconductor device includes first and second cell arrays and a first converter circuit. The first cell array includes a first cell and a second cell in the same row, and the second cell array includes third and fourth cells in the same row. The first cell is electrically connected to first and second wirings, the second cell is electrically connected to the first and third wirings, the third cell is electrically connected to fourth and sixth wirings, and the fourth cell is electrically connected to fifth and seventh wirings. The sixth wiring is electrically connected to the seventh wiring. The first to fourth cells each have a function of outputting current corresponding to a product of retained data and input data. Specifically, the first cell, the second cell, the third cell, and the fourth cell output current to the second wiring, the third wiring, the sixth wiring, and the seventh wiring, respectively. The first converter circuit has a function of making data corresponding to a total amount of current flowing through the second and third wirings flow to the fourth and fifth wirings, respectively.

公开(公告)号：US20240134605A1

公开(公告)日：2024-04-25

申请号：US18278451

申请日：2022-02-24

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Kazuki TSUDA ,  Satoru OHSHITA ,  Hidefumi RIKIMARU

IPC: G06F7/523 ,  G06F7/50 ,  G09G3/3208 ,  G11C11/405 ,  H10B12/00 ,  H10K59/121

CPC classification number: G06F7/523 ,  G06F7/50 ,  G09G3/3208 ,  G11C11/405 ,  H10B12/00 ,  H10K59/1213 ,  H10K59/1216

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a cell array performing a product-sum operation of a first layer and a product-sum operation of a second layer in an artificial neural network, a first circuit from which first data is input to the cell array, and a second circuit to which second data is output from the cell array. The cell array includes a plurality of cells. The cell array includes a first region and a second region. In a first period, the first region is supplied with the t-th (t is a natural number greater than or equal to 2) first data from the first circuit and outputs the t-th second data according to the product-sum operation of the first layer to the second circuit. In the first period, the second region is supplied with the (t+1)-th first data from the first circuit and outputs the (t+1)-th second data according to the product-sum operation of the second layer to the first circuit.

公开(公告)号：US20230065351A1

公开(公告)日：2023-03-02

申请号：US17776696

申请日：2020-11-10

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiromichi GODO ,  Hitoshi KUNITAKE ,  Kazuki TSUDA

IPC: H01L27/11582

Abstract: A novel semiconductor device is provided. A memory string extends in a Z direction. The memory string achieves high-speed operation by using an oxide semiconductor for a semiconductor layer. The memory string includes a MONOS memory cell. A tunnel layer is provided on a control gate side, and a block layer is provided on a semiconductor side. During erase operation, a hole is injected into a charge accumulation layer from the control gate side.

公开(公告)号：US20230044659A1

公开(公告)日：2023-02-09

申请号：US17790517

申请日：2021-01-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiromichi GODO ,  Hitoshi KUNITAKE ,  Kazuki TSUDA

IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11556

Abstract: A novel semiconductor device is provided. A memory string, which extends in the Z direction and includes a conductor and an oxide semiconductor, intersects with a plurality of wirings CG extending in the Y direction. The conductor is placed along a center axis of the memory string, and the oxide semiconductor is concentrically placed outside the conductor. The conductor is electrically connected to the oxide semiconductor. An intersection portion of the memory string and the wiring CG functions as a transistor. In addition, the intersection portion functions as a memory cell.