公开(公告)号：US20130302938A1

公开(公告)日：2013-11-14

申请号：US13875563

申请日：2013-05-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takahiro SATO ,  Takayuki CHO ,  Shunsuke KOSHIOKA ,  Tetsuya OHSHIMA ,  Naoya SAKAMOTO

IPC: H01L29/66 ,  H05K3/06

CPC classification number: H01L29/42384 ,  H01L21/44 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H05K3/06

Abstract: A wiring which is formed using a conductive film containing copper and whose shape is controlled is provided. A transistor including an electrode which is formed in the same layer as the wiring is provided. Further, a semiconductor device including the transistor and the wiring is provided. A resist mask is formed over a second conductive film stacked over a first conductive film; part of the second conductive film and part of the first conductive film are removed with use of the resist mask as a mask so that the first conductive film has a taper angle greater than or equal to 15° and less than or equal to 45°; and the resist mask is removed. The first conductive film contains copper.

Abstract translation: 提供了使用含有铜的导电膜形成并且其形状被控制的布线。 提供了包括与布线形成在同一层中的电极的晶体管。 此外，提供了包括晶体管和布线的半导体器件。 在叠置在第一导电膜上的第二导电膜上形成抗蚀剂掩模; 使用抗蚀剂掩模作为掩模去除第二导电膜的一部分和第一导电膜的一部分，使得第一导电膜具有大于或等于15°且小于或等于45°的锥角; 并且去除抗蚀剂掩模。 第一导电膜含有铜。

公开(公告)号：US20190341502A1

公开(公告)日：2019-11-07

申请号：US16515283

申请日：2019-07-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiro SATO ,  Yasutaka NAKAZAWA ,  Takayuki CHO ,  Shunsuke KOSHIOKA ,  Hajime TOKUNAGA ,  Masami JINTYOU

IPC: H01L29/786 ,  H01L21/02 ,  H01L27/32 ,  H01L29/10 ,  H01L21/465 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L29/24 ,  G02F1/1362 ,  H01L29/423 ,  H01L29/04 ,  H01L21/306

Abstract: A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

公开(公告)号：US20180309056A1

公开(公告)日：2018-10-25

申请号：US16010861

申请日：2018-06-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Takahiro SATO ,  Shunsuke KOSHIOKA ,  Rihito WADA ,  Junko SUZAWA

IPC: H01L51/00 ,  H01L51/52 ,  H01L27/32

CPC classification number: H01L51/003 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1266 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/7869 ,  H01L51/0097 ,  H01L51/5237 ,  H01L51/56 ,  H01L2227/323 ,  H01L2227/326 ,  H01L2251/5338 ,  Y02E10/549 ,  Y02P70/521

Abstract: To provide a highly flexible display device excellent in mass-productivity. A display device includes a flexible substrate, an adhesive layer over the substrate, a resin layer over the adhesive layer, an inorganic insulating layer over the resin layer, a transistor over the inorganic insulating layer, and a display element electrically connected to the transistor. The transistor includes an oxide semiconductor in a channel formation region. The resin layer includes sulfur.

公开(公告)号：US20160035567A1

公开(公告)日：2016-02-04

申请号：US14878399

申请日：2015-10-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiro SATO ,  Yasutaka NAKAZAWA ,  Takayuki CHO ,  Shunsuke KOSHIOKA ,  Hajime TOKUNAGA ,  Masami JINTYOU

IPC: H01L21/02 ,  H01L21/306 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7869 ,  G02F1/136277 ,  G02F1/1368 ,  H01L21/02365 ,  H01L21/02403 ,  H01L21/02422 ,  H01L21/02551 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/30604 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/3248 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78693 ,  H01L29/78696

Abstract: A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

公开(公告)号：US20150270404A1

公开(公告)日：2015-09-24

申请号：US14733489

申请日：2015-06-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiro SATO ,  Yasutaka NAKAZAWA ,  Takayuki CHO ,  Shunsuke KOSHIOKA ,  Hajime TOKUNAGA ,  Masami JINTYOU

IPC: H01L29/786 ,  H01L29/04 ,  G02F1/1362 ,  H01L27/12 ,  H01L27/32 ,  G02F1/1368 ,  H01L29/24 ,  H01L29/423

CPC classification number: H01L29/7869 ,  G02F1/136277 ,  G02F1/1368 ,  H01L21/02365 ,  H01L21/02403 ,  H01L21/02422 ,  H01L21/02551 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/30604 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/3248 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78693 ,  H01L29/78696

Abstract: A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

Abstract translation: 晶体管包括层叠有氧化物半导体膜和氧化膜的多层膜，栅极电极和栅极绝缘膜。 多层膜与栅电极重叠，栅极绝缘膜介于其间。 多层膜具有在氧化物半导体膜的底面和氧化物半导体膜的侧面之间具有第一角度的形状，以及氧化物膜的底面与氧化膜的侧面之间的第二角度。 第一个角度是锐角并小于第二个角度。 此外，制造包括这种晶体管的半导体器件。

公开(公告)号：US20150270403A1

公开(公告)日：2015-09-24

申请号：US14659792

申请日：2015-03-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masahiro KATAYAMA ,  Yasutaka NAKAZAWA ,  Masatoshi YOKOYAMA ,  Masahiko HAYAKAWA ,  Kenichi OKAZAKI ,  Shunsuke KOSHIOKA

IPC: H01L29/786 ,  H01L29/04 ,  G09G5/00 ,  H01L27/12 ,  G06F3/047 ,  H01L29/24 ,  H01L29/45

CPC classification number: H01L29/7869 ,  G06F3/041 ,  G09G3/20 ,  G09G3/3674 ,  G09G3/3677 ,  G09G3/3685 ,  G09G3/3688 ,  G09G5/003 ,  G09G2300/0404 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/0275 ,  H01L27/1225 ,  H01L27/1248 ,  H01L29/78606

Abstract: A semiconductor device including a transistor and a wiring electrically connected to the transistor each of which has excellent electrical characteristics because of specific structures thereover is provided. A first conductive film, a first insulating film over the first conductive film, a second conductive film over the first insulating film, a second insulating film over the second conductive film, a third conductive film electrically connected to the first conductive film through an opening provided in the first insulating film and the second insulating film, and a third insulating film over the third conductive film are provided. The third conductive film includes indium, tin, and oxygen, and the third insulating film includes silicon and nitrogen and the number of ammonia molecules released from the third insulating film is less than or equal to 1×1015 molecules/cm3 by thermal desorption spectroscopy.

Abstract translation: 提供一种包括晶体管和电连接到晶体管的布线的半导体器件，其中由于其特定结构而具有优异的电特性。 第一导电膜，第一导电膜上的第一绝缘膜，第一绝缘膜上的第二导电膜，第二导电膜上的第二绝缘膜，通过开口电连接到第一导电膜的第三导电膜 在第一绝缘膜和第二绝缘膜中，并且在第三导电膜上设置第三绝缘膜。 第三导电膜包括铟，锡和氧，第三绝缘膜包括硅和氮，并且通过热解吸光谱法从第三绝缘膜释放的氨分子的数量小于或等于1×1015分子/ cm 3。

公开(公告)号：US20150140734A1

公开(公告)日：2015-05-21

申请号：US14585918

申请日：2014-12-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takayuki CHO ,  Shunsuke KOSHIOKA ,  Masatoshi YOKOYAMA ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78693 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

Abstract: To provide a highly reliable semiconductor device which includes a transistor including an oxide semiconductor, in a semiconductor device including a staggered transistor having a bottom-gate structure provided over a glass substrate, a gate insulating film in which a first gate insulating film and a second gate insulating film, whose compositions are different from each other, are stacked in this order is provided over a gate electrode layer. Alternatively, in a staggered transistor having a bottom-gate structure, a protective insulating film is provided between a glass substrate and a gate electrode layer. A metal element contained in the glass substrate has a concentration lower than or equal to 5×1018 atoms/cm3 at the interface between the first gate insulating film and the second gate insulating film or the interface between the gate electrode layer and a gate insulating film.

Abstract translation: 为了提供一种高可靠性的半导体器件，其包括具有氧化物半导体的晶体管，在包括设置在玻璃基板上的具有底栅结构的交错晶体管的半导体器件中，栅极绝缘膜，其中第一栅极绝缘膜和第二栅极绝缘膜 其栅极绝缘膜的组成彼此不同，按栅极电极层设置。 或者，在具有底栅结构的交错晶体管中，在玻璃基板和栅电极层之间设置保护绝缘膜。 包含在玻璃基板中的金属元素在第一栅极绝缘膜和第二栅极绝缘膜之间的界面处或者栅极电极层和栅极绝缘膜之间的界面处具有低于或等于5×1018原子/ cm3的浓度 。

公开(公告)号：US20150111340A1

公开(公告)日：2015-04-23

申请号：US14589395

申请日：2015-01-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiro SATO ,  Takayuki CHO ,  Shunsuke KOSHIOKA ,  Tetsuya OHSHIMA ,  Naoya SAKAMOTO

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/44

CPC classification number: H01L29/42384 ,  H01L21/44 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H05K3/06

Abstract: A wiring which is formed using a conductive film containing copper and whose shape is controlled is provided. A transistor including an electrode which is formed in the same layer as the wiring is provided. Further, a semiconductor device including the transistor and the wiring is provided. A resist mask is formed over a second conductive film stacked over a first conductive film; part of the second conductive film and part of the first conductive film are removed with use of the resist mask as a mask so that the first conductive film has a taper angle greater than or equal to 15° and less than or equal to 45′; and the resist mask is removed. The first conductive film contains copper.

Abstract translation: 提供了使用含有铜的导电膜形成并且其形状被控制的布线。 提供了包括与布线形成在同一层中的电极的晶体管。 此外，提供了包括晶体管和布线的半导体器件。 在层叠在第一导电膜上的第二导电膜上形成抗蚀剂掩模; 使用抗蚀剂掩模作为掩模去除第二导电膜的一部分和第一导电膜的一部分，使得第一导电膜具有大于或等于15°且小于或等于45'的锥角; 并且去除抗蚀剂掩模。 第一导电膜含有铜。