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    DISPLAY DEVICE AND ELECTRONIC DEVICE
    13.
    发明申请
    DISPLAY DEVICE AND ELECTRONIC DEVICE 有权

    公开(公告)号：US20250120277A1

    公开(公告)日：2025-04-10

    申请号：US18985487

    申请日：2024-12-18

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takashi NAKAGAWA ,  Hidetomo KOBAYASHI ,  Hideaki SHISHIDO

    IPC: G09G3/3233 ,  G09G3/32

    Abstract: A display device with high luminance is provided. A pixel includes a light-emitting device, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor. One electrode of the light-emitting device is electrically connected to one of a source and a drain of the first transistor. A gate of the first transistor is electrically connected to one electrode of the first capacitor and one of a source and a drain of the second transistor. The other of the source and the drain of the first transistor is electrically connected to one electrode of the second capacitor. One electrode of the second capacitor is electrically connected to a first wiring having a function of supplying a first potential. The other electrode of the second capacitor is electrically connected to the other electrode of the first capacitor, one of a source and a drain of the third transistor, and one of a source and a drain of the fourth transistor.

    DISPLAY DEVICE
    16.
    发明申请
    DISPLAY DEVICE 有权

    公开(公告)号：US20220230573A1

    公开(公告)日：2022-07-21

    申请号：US17609497

    申请日：2020-04-28

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Takashi NAKAGAWA ,  Takayuki IKEDA ,  Hidetomo KOBAYASHI ,  Hideaki SHISHIDO ,  Shuichi KATSUI ,  Kiyotaka KIMURA

    IPC: G09G3/20

    Abstract: A display device with a narrower frame can be provided. In the display device, a first layer, a second layer, and a third layer are provided to be stacked. The first layer includes a gate driver circuit and a data driver circuit, the second layer includes a demultiplexer circuit, and the third layer includes a display portion. In the display portion, pixels are arranged in a matrix, an input terminal of the demultiplexer circuit is electrically connected to the data driver circuit, and an output terminal of the demultiplexer circuit is electrically connected to some of the pixels. The gate driver circuit and the data driver circuit are provided to include a region overlapping some of the pixels. The gate driver circuit and the data driver circuit have a region where they are not strictly separated from each other and overlap each other. Five or more gate driver circuits and five or more data driver circuits can be provided.

    IMAGING DEVICE, OPERATION METHOD THEREOF, AND ELECTRONIC DEVICE
    17.
    发明申请
    IMAGING DEVICE, OPERATION METHOD THEREOF, AND ELECTRONIC DEVICE 有权

    公开(公告)号：US20210202549A1

    公开(公告)日：2021-07-01

    申请号：US17057526

    申请日：2019-06-11

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Seiichi YONEDA ,  Hidetomo KOBAYASHI ,  Takashi NAKAGAWA ,  Yusuke NEGORO ,  Shunpei YAMAZAKI

    IPC: H01L27/146 ,  H04N5/378 ,  H04N5/353 ,  H04N5/369

    Abstract: An imaging device that can obtain imaging data corresponding to high-resolution images in a short period of time is provided. The imaging device includes a pixel including a photoelectric conversion element and n (n is an integer more than 2 inclusive) retention circuits. The photoelectric conversion element and the n retention circuits are stacked. One electrode of the photoelectric conversion element is electrically connected to the first to n-th retention circuits. The retention circuits include OS transistors with an extremely low off-state current feature, and can retain imaging data for a long time. In the first to n-th periods, the imaging device obtains the first to n-th imaging data and retains it in the first to n-th retention circuits. Then, the first to n-th imaging data retained in the first to n-th retention circuits are read out. The read imaging data is output outside the imaging data through AD conversion.

    SEMICONDUCTOR DEVICE, DISPLAY SYSTEM, AND ELECTRONIC DEVICE
    19.
    发明申请
    SEMICONDUCTOR DEVICE, DISPLAY SYSTEM, AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20190229216A1

    公开(公告)日：2019-07-25

    申请号：US16375135

    申请日：2019-04-04

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takashi NAKAGAWA ,  Yoshiyuki KUROKAWA ,  Munehiro KOZUMA

    IPC: H01L29/786 ,  H03K19/177 ,  H03K19/00 ,  H01L27/28 ,  H01L29/16 ,  H01L27/12 ,  H01L29/24

    Abstract: A novel semiconductor device is provided. The semiconductor device includes a programmable logic device including a programmable logic element, a control circuit, and a detection circuit. The programmable logic device includes a plurality of contexts. The control circuit is configured to control selection of the contexts. The detection circuit is configured to output a signal corresponding to the amount of radiation. The control circuit is configured to switch between a first mode and a second mode in accordance with the signal corresponding to the amount of radiation. The first mode is a mode in which the programmable logic device performs processing by a multi-context method, and the second mode is a mode in which the programmable logic device performs processing using a majority signal of signals output from the logic element multiplexed by the plurality of contexts.

    CIRCUIT, DRIVING METHOD THEREOF, AND SEMICONDUCTOR DEVICE
    20.
    发明申请
    CIRCUIT, DRIVING METHOD THEREOF, AND SEMICONDUCTOR DEVICE 审中-公开
    电路，其驱动方法和半导体器件

    公开(公告)号：US20160379564A1

    公开(公告)日：2016-12-29

    申请号：US15183892

    申请日：2016-06-16

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hiroki INOUE ,  Yoshiyuki KUROKAWA ,  Takashi NAKAGAWA ,  Fumika AKASAWA

    IPC: G09G3/3241

    CPC classification number: G05F3/262 ,  G05F3/26 ,  G09G3/2011 ,  G09G2300/0417 ,  G09G2310/027 ,  G09G2310/0272 ,  G09G2330/021 ,  G11C27/024 ,  H01L27/1225

    Abstract: A circuit includes a current mirror circuit (CM circuit) including first and second transistors, a third transistor whose drain is electrically connected to a drain of the second transistor, a switch controlling the current output from the circuit, and first and second memory circuits. A reference current of the CM circuit is input to a drain of the first transistor; a current that is a copy of the reference current is output from the drain of the second transistor. When a current is output from the circuit, the reference current is not input to the CM circuit. A drain current corresponding to a voltage stored in the first memory circuit flows through the second transistor; a drain current corresponding to a voltage stored in the second memory circuit flows through the third transistor. The difference between the two drain currents corresponds to the output current of the circuit.

    Abstract translation: 电路包括包括第一和第二晶体管的电流镜电路（CM电路），漏极电连接到第二晶体管的漏极的第三晶体管，控制来自电路的电流输出的开关以及第一和第二存储器电路。 CM电路的参考电流被输入到第一晶体管的漏极; 作为参考电流的副本的电流从第二晶体管的漏极输出。 当从电路输出电流时，参考电流不输入到CM电路。 与存储在第一存储器电路中的电压相对应的漏极电流流过第二晶体管; 与存储在第二存储器电路中的电压相对应的漏极电流流过第三晶体管。 两个漏极电流之间的差值对应于电路的输出电流。

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