公开(公告)号：US09202925B2

公开(公告)日：2015-12-01

申请号：US14278234

申请日：2014-05-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yutaka Okazaki ,  Hidekazu Miyairi

IPC: H01L29/10 ,  H01L29/786 ,  H01L21/822 ,  H01L27/06 ,  H01L29/423

CPC classification number: H01L29/78606 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78696

Abstract: A structure is employed in which a first protective insulating layer; an oxide semiconductor layer over the first protective insulating layer; a source electrode and a drain electrode that are electrically connected to the oxide semiconductor layer; a gate insulating layer that is over the source electrode and the drain electrode and overlaps with the oxide semiconductor layer; a gate electrode that overlaps with the oxide semiconductor layer with the gate insulating layer provided therebetween; and a second protective insulating layer that covers the source electrode, the drain electrode, and the gate electrode are included. Furthermore, the first protective insulating layer and the second protective insulating layer each include an aluminum oxide film that includes an oxygen-excess region, and are in contact with each other in a region where the source electrode, the drain electrode, and the gate electrode are not provided.

Abstract translation: 采用其中第一保护绝缘层的结构; 在所述第一保护绝缘层上的氧化物半导体层; 与氧化物半导体层电连接的源电极和漏电极; 栅极绝缘层，位于源电极和漏电极之上并与氧化物半导体层重叠; 与所述氧化物半导体层重叠的栅电极，其间设置有所述栅极绝缘层; 并且包括覆盖源电极，漏电极和栅电极的第二保护绝缘层。 此外，第一保护绝缘层和第二保护绝缘层各自包括氧化物膜，该氧化铝膜包括氧过剩区域，并且在源电极，漏电极和栅电极的区域中彼此接触 没有提供

公开(公告)号：US12074224B2

公开(公告)日：2024-08-27

申请号：US17591690

申请日：2022-02-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshinobu Asami ,  Yutaka Okazaki ,  Satoru Okamoto ,  Shinya Sasagawa

IPC: H01L29/786 ,  C23C16/40 ,  C23C16/455 ,  H01L21/475 ,  H01L21/4757 ,  H01L21/67 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7869 ,  C23C16/40 ,  C23C16/45531 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/67207 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/0649 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262

Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.

公开(公告)号：US20230230979A1

公开(公告)日：2023-07-20

申请号：US18125426

申请日：2023-03-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Okazaki ,  Tomoaki Moriwaka ,  Shinya Sasagawa ,  Takashi Ohtsuki

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L21/768

CPC classification number: H01L27/124 ,  H01L27/1255 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/78654 ,  H01L29/7869 ,  H01L21/76849 ,  H01L23/53223

Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

公开(公告)号：US11616085B2

公开(公告)日：2023-03-28

申请号：US17557355

申请日：2021-12-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Okazaki ,  Tomoaki Moriwaka ,  Shinya Sasagawa ,  Takashi Ohtsuki

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L21/768 ,  H01L23/532

Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

公开(公告)号：US11211408B2

公开(公告)日：2021-12-28

申请号：US16863291

申请日：2020-04-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Okazaki ,  Tomoaki Moriwaka ,  Shinya Sasagawa ,  Takashi Ohtsuki

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L21/768 ,  H01L23/532

Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

公开(公告)号：US10522690B2

公开(公告)日：2019-12-31

申请号：US15908215

申请日：2018-02-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Okazaki ,  Daisuke Matsubayashi ,  Yuichi Sato

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/45 ,  H01L21/441 ,  H01L29/78 ,  H01L27/12

Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first insulating layer is deposited over a substrate. A first oxide insulating layer and an oxide semiconductor layer are deposited over the first insulating layer. A second oxide insulating layer is deposited over the oxide semiconductor layer and the first insulating layer. A second insulating layer and a first conductive layer are deposited over the second oxide insulating layer. A gate electrode layer, a gate insulating layer, and a third oxide insulating layer are formed by etching. A sidewall insulating layer including a region in contact with a side surface of the gate electrode layer is formed. A second conductive layer is deposited over the gate electrode layer, the sidewall insulating layer, the oxide semiconductor layer, and the first insulating layer. A third conductive layer is deposited over the second conductive layer. A low-resistance region is formed in the oxide semiconductor layer by performing heat treatment. An element contained in the second conductive layer moves from the second conductive layer to the oxide semiconductor layer side by performing the heat treatment. An element contained in the oxide semiconductor layer moves from the oxide semiconductor layer to the third conductive layer side by performing the heat treatment.

公开(公告)号：US10483402B2

公开(公告)日：2019-11-19

申请号：US15474082

申请日：2017-03-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Daisuke Matsubayashi ,  Yutaka Okazaki

IPC: H01L29/786 ,  H01L29/78

Abstract: The semiconductor device includes a transistor including an oxide semiconductor film having a channel formation region, a gate insulating film, and a gate electrode layer. In the transistor, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the thickness of the gate insulating film is large (equivalent oxide thickness which is obtained by converting into a thickness of silicon oxide containing nitrogen is 5 nm or more and 50 nm or less, preferably 10 nm or more and 40 nm or less). Alternatively, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the resistivity of the source region and the drain region is 1.9×10−5 Ω·m or more and 4.8×10−3 Ω·m or less.

公开(公告)号：US10249651B2

公开(公告)日：2019-04-02

申请号：US15911708

申请日：2018-03-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichi Koezuka ,  Naoto Yamade ,  Yuhei Sato ,  Yutaka Okazaki ,  Shunpei Yamazaki

IPC: H01L21/00 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L21/383 ,  H01L21/44 ,  H01L21/477 ,  H01L21/02

Abstract: A semiconductor device using an oxide semiconductor is provided with stable electric characteristics to improve the reliability. In a manufacturing process of a transistor including an oxide semiconductor film, an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a first crystalline oxide semiconductor film) is formed; oxygen is added to the oxide semiconductor film to amorphize at least part of the oxide semiconductor film, so that an amorphous oxide semiconductor film containing an excess of oxygen is formed; an aluminum oxide film is formed over the amorphous oxide semiconductor film; and heat treatment is performed thereon to crystallize at least part of the amorphous oxide semiconductor film, so that an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a second crystalline oxide semiconductor film) is formed.

公开(公告)号：US10141452B2

公开(公告)日：2018-11-27

申请号：US15864033

申请日：2018-01-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo Ito ,  Daisuke Matsubayashi ,  Masaharu Nagai ,  Yoshiaki Yamamoto ,  Takashi Hamada ,  Yutaka Okazaki ,  Shinya Sasagawa ,  Motomu Kurata ,  Naoto Yamade

IPC: H01L29/786 ,  H01L21/46 ,  H01L27/12 ,  H01L29/66 ,  H01L21/425 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/24 ,  H01L29/778

Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

公开(公告)号：US10014413B2

公开(公告)日：2018-07-03

申请号：US15618480

申请日：2017-06-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yutaka Okazaki

IPC: H01L29/12 ,  H01L29/10 ,  H01L29/786 ,  H01L29/51 ,  H01L27/105 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L29/78606 ,  H01L27/1052 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device that includes an oxide semiconductor and is miniaturized while keeping good electrical properties. In the semiconductor device, an oxide semiconductor layer filling a groove is surrounded by insulating layers including an aluminum oxide film containing excess oxygen. Excess oxygen contained in the aluminum oxide film is supplied to the oxide semiconductor layer, in which a channel is formed, by heat treatment in a manufacturing process of the semiconductor device. Moreover, the aluminum oxide film forms a barrier against oxygen and hydrogen, which inhibits the removal of oxygen from the oxide semiconductor layer surrounded by the insulating layers including an aluminum oxide film and the entry of impurities such as hydrogen in the oxide semiconductor layer. Thus, a highly purified intrinsic oxide semiconductor layer can be obtained. The threshold voltage is controlled effectively by gate electrode layers formed over and under the oxide semiconductor layer.