公开(公告)号：US5978267A

公开(公告)日：1999-11-02

申请号：US175647

申请日：1998-10-20

申请人： Pau-Ling Chen ,  Michael Van Buskirk ,  Shane C. Hollmer ,  Michael S. C. Chung ,  Binh Quang Le ,  Vincent Leung ,  Shoichi Kawamura ,  Masaru Yano

发明人： Pau-Ling Chen ,  Michael Van Buskirk ,  Shane C. Hollmer ,  Michael S. C. Chung ,  Binh Quang Le ,  Vincent Leung ,  Shoichi Kawamura ,  Masaru Yano

IPC分类号： G11C16/02 ,  G11C7/12 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C7/12

摘要： In the programming of a non-volatile memory device, such as a NAND flash memory device 100, a positive bias voltage V.sub.bias is applied to a bit line 44 to set a respective memory gate 44a in a programmed state. In a further embodiment, the positive bias voltage V.sub.bias is obtained by dividing the select drain gate voltage V.sub.cc using two resistors 56 and 58 connected in series.

摘要翻译： 在非易失性存储器件（例如NAND闪速存储器件100）的编程中，将正偏置电压Vbias施加到位线44以将相应的存储器栅极44a设置为编程状态。 在另一实施例中，通过使用串联连接的两个电阻器56和58分压选择漏极栅极电压Vcc来获得正偏置电压Vbias。

公开(公告)号：US5638326A

公开(公告)日：1997-06-10

申请号：US630919

申请日：1996-04-05

申请人： Shane C. Hollmer ,  Pau-Ling Chen ,  Binh Q. Le

发明人： Shane C. Hollmer ,  Pau-Ling Chen ,  Binh Q. Le

IPC分类号： G11C7/14 ,  G11C16/28 ,  G11C7/00

CPC分类号： G11C7/14 ,  G11C16/28

摘要： A flash memory including a page buffer with bias circuitry and a reference array enabling reading and verifying values stored on a word line of memory cells in parallel using the page buffer irrespective of temperature, Vcc, and process variations. The bias circuitry includes a cascode transistor having a source connected to the reference cell array which provides a single reference signal. The bias cascode couples the reference signal to an input of a bias inverter in the bias generator, while a bias load transistor in the bias generator couples Vcc to the bias inverter input. The page buffer includes a set of latches that are each coupled to a memory cell by a cascode. A first inverter in each latch has transistors with sizes matching the transistors in the bias inverter. A latch load transistor is connected between a pull-up and pull-down transistor of a second inverter in each latch and is sized to match the bias load transistor. Gates of the bias load transistor and the latch load transistor are both coupled to the output of the bias inverter enabling the first inverter of each latch to have an input mirroring the input of the bias inverter.

摘要翻译： 包括具有偏置电路的页缓冲器和参考阵列的闪速存储器，其能够使用页缓冲器并行读取和验证存储单元的字线上的值，而与温度，Vcc和工艺变化无关。 偏置电路包括具有连接到参考单元阵列的源的共源共栅晶体管，其提供单个参考信号。 偏置共源共栅将参考信号耦合到偏置发生器中的偏置反相器的输入，而偏置发生器中的偏置负载晶体管将Vcc耦合到偏置反相器输入。 页面缓冲器包括一组锁存器，每个锁存器通过级联耦合到存储器单元。 每个锁存器中的第一个反相器具有与偏置反相器中的晶体管尺寸匹配的晶体管。 锁存器负载晶体管连接在每个锁存器中的第二反相器的上拉和下拉晶体管之间，并且其大小适于匹配偏置负载晶体管。 偏置负载晶体管和锁存负载晶体管的栅极都耦合到偏置反相器的输出，使得每个锁存器的第一反相器具有镜像偏置反相器的输入的输入。

公开(公告)号：US06950336B2

公开(公告)日：2005-09-27

申请号：US10340342

申请日：2003-01-10

申请人： David Sowards ,  Trevor Blyth ,  Shane C. Hollmer

发明人： David Sowards ,  Trevor Blyth ,  Shane C. Hollmer

IPC分类号： G11C16/04 ,  G11C16/08

CPC分类号： G11C16/0408 ,  G11C16/0425 ,  G11C16/08

摘要： An emulated EEPROM memory array is disclosed based on non-volatile floating gate memory cells, such as Flash cells, where a small group of bits share a common source line and common row lines, so that the small group of bits may be treated as a group during program and erase modes to control the issues of program disturb and effective endurance. The bits common to the shared source line make up the emulated EEPROM page which is the smallest unit that can be erased and reprogrammed, without disturbing other bits. The memory array is physically divided up into groups of columns. One embodiment employs four memory arrays, each consisting of 32 columns and 512 page rows (all four arrays providing a total of 1024 pages with each page having 8 bytes or 64 bits). A global row decoder decodes the major rows and a page row driver and a page source driver enable the individual rows and sources that make up a given array. The page row drivers and page source drivers are decoded by a page row/source supply decoder, based on the addresses to be accessed and the access mode (erase, program or read).

摘要翻译： 公开了一种基于诸如闪存单元的非易失性浮动栅极存储器单元的模拟EEPROM存储器阵列，其中一小组位共享公共源极线和公共行线，使得该小组位可被视为 在编程和擦除模式下组合，以控制程序干扰和有效耐力的问题。 共享源线通用的位构成仿真EEPROM页面，它是可以擦除和重新编程的最小单元，而不会干扰其他位。 存储器阵列在物理上分成几组。 一个实施例采用四个存储器阵列，每个存储器阵列由32列和512页行组成（所有四个阵列提供总共1024页，每页具有8字节或64位）。 全局行解码器对主要行进行解码，并且页面行驱动程序和页面源驱动程序启用组成给定数组的各个行和源。 基于要访问的地址和访问模式（擦除，编程或读取），页面行驱动器和页面源驱动器由页面行/源供应解码器进行解码。

公开(公告)号：US06525966B1

公开(公告)日：2003-02-25

申请号：US10010985

申请日：2001-12-05

申请人： Shane C. Hollmer ,  Joseph G. Pawletko ,  Binh Quang Le

发明人： Shane C. Hollmer ,  Joseph G. Pawletko ,  Binh Quang Le

IPC分类号： G11C1606

CPC分类号： G11C16/26 ,  G11C16/06

摘要： Method and apparatus for a memory circuit having a sense amplifier circuit having a sensing amplifier connected to read the data content output of a memory cell where the sense amplifier circuit includes a current source transistor having a gate terminal and having a drain terminal connected to a voltage supply and having a source terminal connected to the sensing amplifier, with a selectable source current in order to account for variation from a desired source current due to variations in the designed source current transistor performance parameters.

摘要翻译： 一种具有读出放大器电路的存储电路的方法和装置，该读出放大器电路具有连接到读出存储单元的数据内容输出的感测放大器，其中读出放大器电路包括具有栅极端子并具有连接到电压的漏极端子的电流源晶体管 提供并具有连接到感测放大器的源极端子，具有可选择的源极电流，以便考虑到由于设计的源极电流晶体管性能参数的变化而导致的期望源极电流的变化。

公开(公告)号：US06373742B1

公开(公告)日：2002-04-16

申请号：US09689036

申请日：2000-10-12

申请人： Kazuhiro Kurihara ,  Shane C. Hollmer ,  Pau-Ling Chen

发明人： Kazuhiro Kurihara ,  Shane C. Hollmer ,  Pau-Ling Chen

IPC分类号： G11C506

CPC分类号： G11C8/10 ,  G11C5/025 ,  G11C5/063

摘要： A decoder for decoding from two sides of a memory array. The decoder is positioned on two sides of the memory array. The decoder includes driver circuits that are connected to routing lines from the memory array. To reduce the size of the decoder, some of the routing lines extend from one side of the memory array and the remaining routing lines extend from the other side of the memory array.

摘要翻译： 一种用于从存储器阵列的两侧进行解码的解码器。 解码器位于存储器阵列的两侧。 解码器包括从存储器阵列连接到路由线路的驱动器电路。 为了减小解码器的大小，一些路由线从存储器阵列的一侧延伸，并且剩余的路由线从存储器阵列的另一侧延伸。

公开(公告)号：US06215702B1

公开(公告)日：2001-04-10

申请号：US09504696

申请日：2000-02-16

申请人： Narbeh Derhacobian ,  Shane C. Hollmer ,  Ravi S. Sunkavalli

发明人： Narbeh Derhacobian ,  Shane C. Hollmer ,  Ravi S. Sunkavalli

IPC分类号： G11C1134

CPC分类号： H01L29/7923 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/14

摘要： A method of erasing a memory cell that has a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains an initial amount of charge. The method includes applying a first cycle of voltages across the gate and the first region so that the first amount of charge is removed from the charge trapping region. A second amount of charge is written into the charge trapping region and subsequently a second cycle of one or more voltages is applied across the gate and the first region so that the second amount of charge is removed from the charge trapping region, wherein the initial applied voltage of the second cycle of voltages is equal to the final applied voltage of the first cycle of voltages.

摘要翻译： 一种擦除具有第一区域和第二区域以及沟道上方的栅极的存储单元的方法，以及包含初始电荷量的电荷捕获区域。 该方法包括跨越栅极和第一区域施加电压的第一周期，使得从电荷俘获区域去除第一电荷量。 第二量的电荷被写入电荷俘获区域中，随后在栅极和第一区域两端施加一个或多个电压的第二周期，使得从电荷俘获区域去除第二电荷量，其中初始施加 电压的第二周期的电压等于第一周期电压的最终施加电压。

公开(公告)号：US6009014A

公开(公告)日：1999-12-28

申请号：US90296

申请日：1998-06-03

申请人： Shane C. Hollmer ,  Chung-You Hu ,  Binh Q. Le ,  Pau-ling Chen ,  Jonathan Su ,  Ravi Gutala ,  Colin Bill

发明人： Shane C. Hollmer ,  Chung-You Hu ,  Binh Q. Le ,  Pau-ling Chen ,  Jonathan Su ,  Ravi Gutala ,  Colin Bill

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C16/06

CPC分类号： G11C16/3445 ,  G11C16/0483 ,  G11C16/344

摘要： The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates of each transistor during an erase verify. The bias voltage is at least equal to the erased threshold voltage of the worst case transistor to ensure proper erase verification. If all transistors are not erased, then another erase operation is performed. Erasing is repeated until the erase verify operation indicates that all transistors are properly erased. By erasing and verifying according to the present invention, the NAND array is completely and properly erased while minimizing overerasing the array.

摘要翻译： 本发明提供了一种验证NAND串中的所有闪存EEPROM晶体管是否被适当地擦除，而不会通过向NAND阵列的底部选择栅极的源施加偏置电压而对其进行过载并向非线性擦除验证电压施加非负的擦除验证电压 在擦除验证期间每个晶体管的控制栅极。 偏置电压至少等于最坏情况晶体管的擦除阈值电压，以确保正确的擦除验证。 如果所有晶体管都不被擦除，则执行另一个擦除操作。 重复擦除直到擦除验证操作指示所有晶体管被正确擦除。 通过根据本发明的擦除和验证，NAND阵列被完全和适当地擦除，同时使阵列过度减少。

公开(公告)号：US6005804A

公开(公告)日：1999-12-21

申请号：US993634

申请日：1997-12-18

申请人： Shane C. Hollmer ,  Binh Quang Le ,  Pau-ling Chen

发明人： Shane C. Hollmer ,  Binh Quang Le ,  Pau-ling Chen

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/00

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： An EEPROM NAND array has floating gate memory cells coupled in series, each having a control gate, a floating gate, a body region, and an insulating layer between the floating gate and the body region. A negative charge pump is coupled to the body region. In programming, the body region of the memory cell selected for programming is biased to a negative voltage by the negative charge pump while the control gate of the memory cell is biased to a predetermined positive voltage sufficient to induce Fowler-Nordheim tunneling from the body region into the floating gate. The present invention allows the programming voltage requirement at the control gate of a NAND EEPROM memory cell to be significantly reduced which allows for the peripheral voltage delivery circuitry in NAND EEPROM arrays to be designed for lower voltages than for conventional NAND EEPROM arrays.

摘要翻译： EEPROM NAND阵列具有串联耦合的浮动栅极存储单元，每个浮动栅极存储单元在浮置栅极和体区之间具有控制栅极，浮动栅极，体区域和绝缘层。 负电荷泵耦合到身体区域。 在编程中，选择用于编程的存储单元的主体区域被负电荷泵偏置到负电压，而存储单元的控制栅极被偏置到预定的正电压以足以引导来自身体区域的Fowler-Nordheim隧穿 进入浮动门。 本发明允许NAND EEPROM存储单元的控制栅极上的编程电压要求显着降低，这允许NAND EEPROM阵列中的外围电压传送电路被设计为比传统的NAND EEPROM阵列更低的电压。

公开(公告)号：US5995417A

公开(公告)日：1999-11-30

申请号：US175646

申请日：1998-10-20

申请人： Pau-Ling Chen ,  Michael S. C. Chung ,  Shane C. Hollmer ,  Vincent Leung ,  Binh Quang Le ,  Masaru Yano

发明人： Pau-Ling Chen ,  Michael S. C. Chung ,  Shane C. Hollmer ,  Vincent Leung ,  Binh Quang Le ,  Masaru Yano

IPC分类号： G11C16/02 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3445 ,  G11C16/16 ,  G11C16/344

摘要： A non-volatile memory device includes a plurality of MOS transistors 34 and 36 connected to respective word lines 16 and 18 to allow individual pages of memory stored in the memory cells 8a, 10a and 8b, 10b on the respective word lines 16 and 18 to be erased and erase verified. A method of erasing a page of memory cells includes the steps of applying an erase voltage to one of the MOS transistors 16 and 18 to erase the page of memory cells along the respective word line, and applying an initial erase-inhibit floating voltage to other MOS transistors which are connected to the word lines unselected for page erase. In an erase verify mode, an erase verify voltage is applied to the word line which was selected for page erase in the erase mode, and an erase verify unselect voltage is applied to the word lines which was not selected for page erase.

摘要翻译： 非易失性存储器件包括连接到各个字线16和18的多个MOS晶体管34和36，以允许存储在相应字线16和18上的存储器单元8a，10a和8b，10b中的存储器的各页 被擦除和擦除验证。 擦除一页存储单元的方法包括以下步骤：将擦除电压施加到MOS晶体管16和18中的一个以擦除沿着相应字线的存储单元的页面，并将初始擦除禁止浮动电压施加到其他 连接到未选择用于页面擦除的字线的MOS晶体管。 在擦除验证模式下，擦除验证电压被施加到在擦除模式下被选择用于页擦除的字线，并且擦除验证未选择电压被施加到未被选择用于页擦除的字线。

公开(公告)号：US5828601A

公开(公告)日：1998-10-27

申请号：US160582

申请日：1993-12-01

申请人： Shane C. Hollmer ,  Lee E. Cleveland

发明人： Shane C. Hollmer ,  Lee E. Cleveland

IPC分类号： G11C17/00 ,  G05F3/24 ,  G11C11/56 ,  G11C16/02 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C11/5642 ,  G05F3/24 ,  G11C11/5621 ,  G11C11/5628 ,  G11C2211/5634

摘要： A programmable reference used to identify a state of an array cell in a multi-density or low voltage supply flash EEPROM memory array. The programmable reference includes one or more reference cells, each reference cell having a floating gate which is programmed to control its threshold value. The array cells are read by applying an identical voltage to the gate of the array cell and the reference cell and comparing outputs to determine the array cell state. During read of an array cell, the programmable reference cell is biased the same as the array cell, so that the difference in threshold values between reference cells and array cells remain constant with a change in V.sub.CC. Circuitry is included for programming the reference cells utilizing a simple resistor ratio. Programming is performed at test time, preferably by the manufacturer, to assure V.sub.CC remains within strict tolerances. The array cells are programmed and read without resistor biasing and under looser tolerances using the reference cells at a later time.

摘要翻译： 用于识别多密度或低电压电源闪存EEPROM存储器阵列中的阵列单元的状态的可编程参考。 可编程参考包括一个或多个参考单元，每个参考单元具有浮动栅极，其被编程以控制其阈值。 通过向阵列单元和参考单元的栅极施加相同的电压来读取阵列单元，并比较输出以确定阵列单元状态。 在阵列单元的读取期间，可编程参考单元被偏置为与阵列单元相同，使得参考单元和阵列单元之间的阈值差随着VCC的变化而保持不变。 包括电路用于使用简单的电阻比来对参考电池进行编程。 编程在测试时间，优选由制造商执行，以确保VCC保持严格的公差。 阵列单元被编程和读取，没有电阻器偏置，并且在稍后的时候使用参考单元在更宽的容限下。