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公开(公告)号：US20180211628A1
公开(公告)日：2018-07-26
申请号：US15500114
申请日：2017-01-18
Inventor： Peng Du
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/20 , G09G3/36 , G09G2310/0267 , G09G2310/0286 , G09G2320/0223 , G11C19/28
Abstract: Disclosed is a gate drive circuit. The circuit includes multiple stages of gate drive units, and a gate drive unit in each stage includes a pull-up control module which outputs a pull-up control signal based on a previous stage of gate drive signal, a first pull-up module connected to the pull-up control module, a boost module connected to the first pull-up module, a second pull-up module connected to the first pull-up module, and a pull-down module connected to the first pull-up module and the second pull-up module.
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公开(公告)号：US10013929B2
公开(公告)日：2018-07-03
申请号：US14436056
申请日：2015-01-21
Inventor： Peng Du , Ming-Hung Shih , Chih-Tsung Kang , Je-Hao Hsu , Qibiao Lv
IPC: G09G3/36 , G02F1/1343 , G02F1/1362 , G02F1/1368
CPC classification number: G09G3/3607 , G02F1/134309 , G02F1/13624 , G02F1/136286 , G02F1/1368 , G02F2001/134345 , G02F2201/121 , G09G3/3655 , G09G3/3688 , G09G2300/0426 , G09G2300/0447
Abstract: The invention provides a thin film transistor (TFT) array substrate and a display panel. The TFT array substrate is disposed with multiple pixels arranged in an array. Each pixel includes first through third sub-pixels sequentially arranged along a first direction. The first through third sub-pixels are connected to a same scan line. The TFT array substrate further is disposed with first through third data lines sequentially arranged along the first direction. The first through third data lines respectively are for driving the first through third sub-pixels. The first sub-pixel includes first and second areas, the second sub-pixel includes third and fourth areas, and the third sub-pixel includes fifth and sixth areas, arranged along a second direction. A voltage difference between a sub-pixel electrode in the sixth area and a common electrode is different from a voltage difference between a sub-pixel electrode in the fifth area and the common electrode.
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公开(公告)号：US09940894B2
公开(公告)日：2018-04-10
申请号：US14777170
申请日：2015-01-22
Inventor： Peng Du
CPC classification number: G09G5/003 , G09G3/20 , G09G2300/0413 , G09G2300/0426 , G09G2300/08 , G09G2300/0819 , G09G2330/04
Abstract: The present embodiment is provided for a circuit of display panel, wherein comprising a signal wire extending along the first direction, a public electrode wire extending along the second direction, a pixel electrode, the first discharge circuit and the second discharge circuit, each signal wire is electrical connecting with the public electrode wire with the first discharge circuit and the second discharge circuit, the first discharge circuit and the second discharge circuit is in series, the pixel electrode is connecting on the intersection point between the first discharge circuit and the second discharge circuit.
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公开(公告)号：US09893097B2
公开(公告)日：2018-02-13
申请号：US14762458
申请日：2015-06-17
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
IPC: H01L27/12 , H01L29/66 , H01L29/786
CPC classification number: H01L27/1288 , H01L27/124 , H01L27/1248 , H01L29/66765 , H01L29/78618 , H01L29/78678
Abstract: An LTPS array substrate and a method for producing the same are proposed. The method includes: forming a gate of a thin-film transistor (TFT) of the LTPS array substrate on a substrate; forming a first insulating layer, a semiconductor layer, and a positive photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a second insulating layer on the substrate of the polycrystalline silicon layer; forming a source and a drain of the TFT on the second insulating layer so that the source and the drain is electrically connected to the polycrystalline silicon layer via a contact hole. The use of masks in types and in numbers in the LTPS technology will be reduced. So, both of the processes and the production costs are reduced.
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公开(公告)号：US09886922B2
公开(公告)日：2018-02-06
申请号：US14906571
申请日：2015-12-30
Inventor： Peng Du
IPC: G09G3/36 , G02F1/1362 , G02F1/1368 , G02F1/1343
CPC classification number: G09G3/3614 , G02F1/134309 , G02F1/136286 , G02F1/1368 , G02F2001/134345 , G09G3/3607 , G09G3/3648 , G09G3/3655 , G09G2300/0439 , G09G2300/0443 , G09G2300/0809 , G09G2310/021 , G09G2320/0209
Abstract: An array substrate is described. The array substrate with a polarity inversion of drive voltage signal in a plurality of data lines comprises a plurality of gate line sets being sequentially arranged, wherein each gate line set comprises two gate lines having an odd gate line and an even gate line respectively; a plurality of data line sets being sequentially arranged and vertically interlaced with the gate line sets, wherein each data line set comprises two data lines having an odd data line and an even data line respectively; wherein a plurality of sub-pixels are sequentially disposed between two adjacent gate line sets, connection positions of a portion of sub-pixels to the odd gate line and the even gate line in one gate line set respectively are changed in a predetermined amount of data line spaced apart.
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Patent Agency Ranking
公开(公告)号：US09563092B2
公开(公告)日：2017-02-07
申请号：US14384157
申请日：2014-09-03
IPC: G02F1/1345
CPC classification number: G02F1/1345
Abstract: A liquid crystal display panel and a fan-out area thereof are provided. The fan-out area is arranged in a peripheral circuit area of the liquid crystal display panel and includes a middle wire and multiple fan-out wires arranged at two sides thereof. The middle wire and the fan-out wires each are disposed with at least one first wire pattern. Along each of directions toward the middle wire, widths of the first wire patterns of different wires are successively increased and/or lengths of the first wire patterns are successively decreased. The first wire patterns of a same wire have same width and length. Accordingly, the present invention can reduce the resistance differences among the wires in the fan-out area, color washout and non-uniform brightness caused by the resistance differences can be relieved or avoided, and is beneficial to the narrow border design of the liquid crystal display panel.
Abstract translation: 提供了一种液晶显示面板及其扇出区域。 扇出区域布置在液晶显示面板的外围电路区域中，并且包括布置在其两侧的中间线和多个扇出线。 中间线和扇出线各自配置有至少一个第一线图案。 沿着朝向中间线的每个方向，不同线的第一线图形的宽度依次增加和/或第一线图案的长度连续减小。 同一根丝线的第一根丝线具有相同的宽度和长度。 因此，本发明可以减小扇出区域中的电线之间的电阻差异，可以缓解或避免由电阻差引起的彩色冲洗和不均匀的亮度，有利于液晶的窄边框设计 显示面板。
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17.发明申请公开(公告)号：US20160291418A1
公开(公告)日：2016-10-06
申请号：US14647803
申请日：2015-04-16
Inventor： Peng Du
IPC: G02F1/1343 , G02F1/1335 , G02F1/1333 , H01L27/12
CPC classification number: G02F1/134309 , G02F1/133345 , G02F1/133514 , G02F2001/133357 , G02F2001/134372 , H01L27/1288
Abstract: The present invention provides an array substrate, a flat display panel and a manufacturing for the same. The array substrate includes a substrate, a common electrode disposed on the substrate, an insulation layer disposed on the common electrode, wherein, the insulation layer includes multiple first regions and multiple second regions, and the first regions and the second regions are disposed alternately, and multiple pixel electrodes respectively disposed on the first regions of the insulation layer. Wherein, a thickness of the first regions and a thickness of the second regions are different. Through above way, the electric field strength between pixel electrodes and the electric field strength above the pixel electrodes can be adjusted in order to increase the display quality of the flat display panel.
Abstract translation: 本发明提供一种阵列基板，平板显示面板及其制造方法。 阵列基板包括基板，设置在基板上的公共电极，设置在公共电极上的绝缘层，其中绝缘层包括多个第一区域和多个第二区域，并且第一区域和第二区域交替设置， 以及分别设置在绝缘层的第一区域上的多个像素电极。 其中，第一区域的厚度和第二区域的厚度不同。 通过上述方式，可以调整像素电极之间的电场强度和像素电极之上的电场强度，以便增加平板显示面板的显示质量。
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18.发明授权LTPS TFT having dual gate structure and method for forming LTPS TFT 有权具有双栅极结构的LTPS TFT和用于形成LTPS TFT的方法公开(公告)号：US09437435B2
公开(公告)日：2016-09-06
申请号：US14415607
申请日：2014-11-14
Inventor： Xiaoxiao Wang , Hsiang Chih Hsiao , Peng Du , Chang-I Su , Hongyuan Xu , Bo Sun
IPC: H01L21/28 , H01L27/12 , H01L29/786 , H01L29/66 , H01L29/49 , H01L29/423
CPC classification number: H01L21/28114 , H01L21/28035 , H01L27/1222 , H01L27/1288 , H01L29/42384 , H01L29/4908 , H01L29/6675 , H01L29/78603 , H01L29/78648 , H01L29/78672
Abstract: The present invention proposes a low temperature poly-silicon thin-film transistor having a dual-gate structure and a method for forming the low temperature poly-silicon thin-film transistor. The low temperature poly-silicon thin-film transistor includes: a substrate, one or more patterned amorphous silicon (a-Si) layers, disposed in a barrier layer on the substrate, for forming a bottom gate, an NMOS disposed on the barrier layer, and a PMOS disposed on the barrier layer. The NMOS comprises a patterned gate electrode (GE) layer as a top gate, and the patterned GE layer and the bottom gate formed by the one or more patterned a-Si layers form a dual-gate structure. The present invention proposes a low temperature poly-silicon thin-film transistor with a more stabilized I-V characteristic, better driving ability, low power consumption, and higher production yield.
Abstract translation: 本发明提出了一种具有双栅极结构的低温多晶硅薄膜晶体管和形成低温多晶硅薄膜晶体管的方法。 低温多晶硅薄膜晶体管包括：基板，设置在基板上的阻挡层中的一个或多个图案化非晶硅（a-Si）层，用于形成底栅，设置在势垒层上的NMOS 和设置在阻挡层上的PMOS。 NMOS包括作为顶栅的图案化栅电极（GE）层，并且由一个或多个图案化a-Si层形成的图案化GE层和底栅形成双栅结构。 本发明提出了具有更稳定的I-V特性，更好的驱动能力，低功耗和更高的产量的低温多晶硅薄膜晶体管。
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公开(公告)号：US20160246124A1
公开(公告)日：2016-08-25
申请号：US14418170
申请日：2015-01-12
Inventor： Peng Du , Ming Hung Shih , Chih Tsung Kang
IPC: G02F1/1343 , G02F1/1333 , G02F1/1368
CPC classification number: G02F1/134309 , G02F1/133371 , G02F1/133707 , G02F1/1368 , G02F2001/134345
Abstract: A liquid crystal display panel and a display device are provided. The liquid crystal display panel comprises a plurality of pixel units arranged as an array. Each pixel unit comprises at least three sub pixels of different colors. In each pixel unit, a primary region of each of some of the sub pixels has a larger brightness than a secondary region thereof, and each of the rest sub pixels has a consistent brightness.
Abstract translation: 提供了一种液晶显示面板和显示装置。 液晶显示面板包括排列成阵列的多个像素单元。 每个像素单元包括至少三个不同颜色的子像素。 在每个像素单元中，一些子像素中的每一个的主区域具有比其次级区域更大的亮度，并且其余子像素中的每一个具有一致的亮度。
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公开(公告)号：US09000435B1
公开(公告)日：2015-04-07
申请号：US14234419
申请日：2013-12-30
Inventor： Peng Du , Minghung Shih
CPC classification number: H01L24/83 , G02F1/136259 , G02F2001/136268 , G09G3/006 , H01L23/481 , H01L24/48 , H01L27/105 , H01L27/124 , H01L27/3223 , H01L2224/48227 , H01L2224/73265 , H01L2224/83191 , H01L2251/568 , H01L2924/10
Abstract: A display device and a testing line repairing method thereof is provided herein and the method comprises steps of: cutting off a connection between a first input end of a first thin film transistor (TFT), a first output end and a testing signal input line; and connecting a first dummy line and a testing signal output line by a laser welding method. The width-to-length ration in the display device of the present disclosure won't be varied and an abnormal display in the light-on testing won't happen.
Abstract translation: 本发明提供一种显示装置及其测试线修复方法，该方法包括以下步骤：切断第一薄膜晶体管（TFT）的第一输入端，第一输出端和测试信号输入线之间的连接; 以及通过激光焊接方法连接第一虚拟线和测试信号输出线。 本公开的显示装置中的宽度与长度比例不会变化，并且不会发生点亮测试中的异常显示。
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