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公开(公告)号：US20160131930A1
公开(公告)日：2016-05-12
申请号：US14411919
申请日：2014-11-19
Inventor： Bo Sun , XiaoLing Zou
IPC: G02F1/1368 , H01L29/786 , H01L27/12 , G02F1/1362 , G02F1/1333
CPC classification number: H01L29/78669 , G02F1/133707 , G02F1/136227 , G02F2001/136222 , H01L27/124 , H01L27/1248
Abstract: A COA substrate is provided including a substrate base, a first metal layer, a first insulating layer, a semiconductor layer, a second metal layer, a color resist layer, and a pixel electrode layer. The surface of the color resist layer is provided with a protrusion and a recess, and the pixel electrode is disposed on the protrusion and the recess. A plurality of protrusions and a plurality of recesses are provided, thereby increasing the display quality of a liquid crystal display device.
Abstract translation: 提供一种COA基板，包括基板基底，第一金属层，第一绝缘层，半导体层，第二金属层，着色抗蚀剂层和像素电极层。 着色层的表面设置有突起和凹部，像素电极配置在突起和凹部上。 提供多个突起和多个凹部，从而提高液晶显示装置的显示质量。
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公开(公告)号：US09995980B2
公开(公告)日：2018-06-12
申请号：US14766761
申请日：2015-04-15
Inventor： Bo Sun
IPC: G02F1/136 , G02F1/1362 , G02F1/1335
CPC classification number: G02F1/136286 , G02F1/133509
Abstract: An LCD panel and an LCD device are provided. The LCD panel includes a first substrate, which includes a first metal layer, a first insulating layer, an active layer, a second metal layer, a second insulating layer, a color barrier layer, a first transparent conductive layer, a planarization layer, and a second transparent conductive layer electrically connected with the first transparent conductive layer sequentially formed. The first metal layer includes scanning lines. Black matrices are arranged on positions corresponding to scanning lines and corresponding to channels.
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公开(公告)号：US10177171B2
公开(公告)日：2019-01-08
申请号：US14915909
申请日：2016-01-29
Inventor： Bo Sun
IPC: H01L27/12 , H01L27/32 , H01L29/41 , H01L29/45 , H01L29/66 , H01L29/78 , G02F1/13 , G02F1/1337 , G02F1/1343 , G02F1/1368 , H01L29/417 , H01L29/786 , G02F1/1362 , G02F1/1333
Abstract: A display panels having a direct contact of the source or drain and pixel electrode. The display panels includes an array substrate. The array substrate includes a substrate and at least one TFT and at least one pixel electrode on the array substrate. The TFT includes a gate, a source, a drain, a gate insulation layer and a trench layer, the trench layer include an AS Island pattern and a doped layer, the source and the drain are arranged on the doped layer, and the AS Island pattern is arranged on the gate insulation layer. The source or the drain directly contacts with the pixel electrode without any material layers provided there between.
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4.发明授权公开(公告)号：US09970978B1
公开(公告)日：2018-05-15
申请号：US15854835
申请日：2017-12-27
Inventor： Bo Sun , Xiaoling Zou
CPC classification number: G01R31/2607 , G01R27/02 , G01R31/26 , H01L51/0031 , H01L51/0545 , H01L51/0558 , H01L51/0566 , H01L51/105
Abstract: A TFT device for measuring a contact resistance and a measurement method for a contact resistance are disclosed. The TFT includes an active layer, a gate electrode and a gate insulation layer. The active layer includes a channel and at least three doping regions. Two of the at least three doping regions is connected through a channel. To measure the contact resistance, two of the at least three doping regions are selected and used as testing points for measuring. The gate electrode is disposed to correspond to the channel. The gate insulation layer insulatively isolates the active layer from the gate electrode. Excellent uniformity can be achieved so that manufacturing, film forming quality, and interface property show similarity to the maximum degree. Accordingly, measurement accuracy is increased, and distribution region can be saved to thereby increase utilization of an experimental region.
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5.发明授权公开(公告)号：US09903904B2
公开(公告)日：2018-02-27
申请号：US14896741
申请日：2015-10-08
Inventor： Bo Sun , Xiaoling Zou
CPC classification number: G01R31/2607 , G01R27/02 , G01R31/26 , H01L51/0031 , H01L51/0545 , H01L51/0558 , H01L51/0566 , H01L51/105
Abstract: TFT device for measuring a contact resistance and measurement method for a contact resistance are disclosed. The TFT includes an active layer, a gate electrode and a gate insulation layer. The active layer includes a channel and at least three doping regions, wherein, two of the at least three doping regions is connected through a channel, when measuring the contact resistance, using two of the at least three doping regions as testing points for measuring. The gate electrode disposed correspondingly to the channel. The gate insulation layer for insulating the active layer from the gate electrode. The uniformity of the present invention is well, the manufacturing process, the film forming quality and the interface property are similar in a maximum degree. Accordingly, a measurement accuracy is increased, saving the distribution region at the same time, increasing the utilization of the experimental region.
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Patent Agency Ranking
公开(公告)号：US09726955B2
公开(公告)日：2017-08-08
申请号：US14430205
申请日：2014-09-11
Inventor： Bo Sun , Hongyuan Xu , Hsiangchih Hsiao , Changi Su , Mian Zeng , Xiaoxiao Wang
IPC: G02F1/1368 , H01L21/12 , G02F1/136 , H01L21/84 , H01L27/12 , G02F1/1335 , G02F1/1343 , H01L21/02 , H01L21/027 , H01L21/285 , H01L29/66 , H01L29/786 , G02F1/1362 , G02F1/1333
CPC classification number: G02F1/1368 , G02F1/133514 , G02F1/134309 , G02F1/13439 , G02F1/136 , G02F1/136227 , G02F2001/133302 , G02F2001/133519 , G02F2001/136222 , H01L21/02422 , H01L21/02532 , H01L21/02592 , H01L21/0273 , H01L21/2855 , H01L21/84 , H01L27/12 , H01L27/1218 , H01L27/1222 , H01L27/1288 , H01L29/66765 , H01L29/78669
Abstract: The present invention provides a manufacture method of a TFT array substrate and a TFT array substrate structure, and the TFT array substrate structure comprises a substrate (1), a first metal electrode (2) on the substrate (1), a gate isolation layer (3) positioned on the substrate (1) and completely covering the first metal electrode (2), an island shaped semiconductor layer (4) on the gate isolation layer (3), a second metal electrode (6) on the gate isolation layer (3) and the island shaped semiconductor layer (4), a protecting layer (8) on the second metal electrode (6), a color resist layer (7) on the protecting layer (8), a protecting layer (12) on the color resist layer (7) and a first pixel electrode layer (9) on the protecting layer (12); a via (81) is formed on the protecting layer (8), the color resist layer (7) and the protecting layer (12), and an organic material layer (10) fills the inside of the via (81).
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公开(公告)号：US20170148409A1
公开(公告)日：2017-05-25
申请号：US14785986
申请日：2015-06-17
Inventor： Bo Sun
IPC: G09G3/36 , G02F1/1343 , G02F1/1368 , G02F1/1362
CPC classification number: G09G3/3696 , G02F1/134309 , G02F1/136286 , G02F1/1368 , G02F2001/134345 , G02F2201/121 , G09G3/3659 , G09G3/3677 , G09G3/3688 , G09G2300/0426 , G09G2300/0447 , G09G2310/0251 , G09G2320/0242 , G09G2320/0247
Abstract: A liquid crystal display panel is disclosed. The liquid crystal display panel comprises a plurality of pixel units, wherein each pixel unit is composed of a first sub pixel unit with a first pixel voltage and a second sub pixel unit with a second pixel voltage which use a same data line while different scanning lines respectively; and wherein the second sub pixel unit is driven during a driving period of the first sub pixel unit. According to the present disclosure, the influence of a second coupling voltage on the LCD during alternating current driving process can be eliminated.
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公开(公告)号：US09577104B2
公开(公告)日：2017-02-21
申请号：US14411919
申请日：2014-11-19
Inventor： Bo Sun , XiaoLing Zou
IPC: G02F1/1337 , H01L29/786 , G02F1/1362 , H01L27/12
CPC classification number: H01L29/78669 , G02F1/133707 , G02F1/136227 , G02F2001/136222 , H01L27/124 , H01L27/1248
Abstract: A COA substrate is provided including a substrate base, a first metal layer, a first insulating layer, a semiconductor layer, a second metal layer, a color resist layer, and a pixel electrode layer. The surface of the color resist layer is provided with a protrusion and a recess, and the pixel electrode is disposed on the protrusion and the recess. A plurality of protrusions and a plurality of recesses are provided, thereby increasing the display quality of a liquid crystal display device.
Abstract translation: 提供一种COA基板，包括基板基底，第一金属层，第一绝缘层，半导体层，第二金属层，着色抗蚀剂层和像素电极层。 着色层的表面设置有突起和凹部，像素电极配置在突起和凹部上。 提供多个突起和多个凹部，从而提高液晶显示装置的显示质量。
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9.发明授权LTPS TFT having dual gate structure and method for forming LTPS TFT 有权具有双栅极结构的LTPS TFT和用于形成LTPS TFT的方法公开(公告)号：US09437435B2
公开(公告)日：2016-09-06
申请号：US14415607
申请日：2014-11-14
Inventor： Xiaoxiao Wang , Hsiang Chih Hsiao , Peng Du , Chang-I Su , Hongyuan Xu , Bo Sun
IPC: H01L21/28 , H01L27/12 , H01L29/786 , H01L29/66 , H01L29/49 , H01L29/423
CPC classification number: H01L21/28114 , H01L21/28035 , H01L27/1222 , H01L27/1288 , H01L29/42384 , H01L29/4908 , H01L29/6675 , H01L29/78603 , H01L29/78648 , H01L29/78672
Abstract: The present invention proposes a low temperature poly-silicon thin-film transistor having a dual-gate structure and a method for forming the low temperature poly-silicon thin-film transistor. The low temperature poly-silicon thin-film transistor includes: a substrate, one or more patterned amorphous silicon (a-Si) layers, disposed in a barrier layer on the substrate, for forming a bottom gate, an NMOS disposed on the barrier layer, and a PMOS disposed on the barrier layer. The NMOS comprises a patterned gate electrode (GE) layer as a top gate, and the patterned GE layer and the bottom gate formed by the one or more patterned a-Si layers form a dual-gate structure. The present invention proposes a low temperature poly-silicon thin-film transistor with a more stabilized I-V characteristic, better driving ability, low power consumption, and higher production yield.
Abstract translation: 本发明提出了一种具有双栅极结构的低温多晶硅薄膜晶体管和形成低温多晶硅薄膜晶体管的方法。 低温多晶硅薄膜晶体管包括：基板，设置在基板上的阻挡层中的一个或多个图案化非晶硅（a-Si）层，用于形成底栅，设置在势垒层上的NMOS 和设置在阻挡层上的PMOS。 NMOS包括作为顶栅的图案化栅电极（GE）层，并且由一个或多个图案化a-Si层形成的图案化GE层和底栅形成双栅结构。 本发明提出了具有更稳定的I-V特性，更好的驱动能力，低功耗和更高的产量的低温多晶硅薄膜晶体管。
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公开(公告)号：US09638975B2
公开(公告)日：2017-05-02
申请号：US14758564
申请日：2015-04-22
Inventor： Hongyuan Xu , Bo Sun
IPC: G02F1/1368 , G02F1/1333 , G02F1/1335 , G02F1/1343 , G02F1/1362
CPC classification number: G02F1/1368 , G02F1/1333 , G02F1/1335 , G02F1/1343 , G02F1/13439 , G02F1/136227 , G02F1/136286 , G02F2001/133302 , G02F2001/133357 , G02F2001/136222 , G02F2001/136295 , G02F2201/121 , G02F2201/123 , G02F2201/52 , G02F2202/02
Abstract: The present invention provides a method for manufacturing a COA liquid crystal panel and a COA liquid crystal panel. The method includes forming a first pixel electrode layer on a color resist layer, forming a planarization layer on the first pixel electrode layer, and forming a second pixel electrode layer that is in engagement with the first pixel electrode layer on the planarization layer so as to achieve planarization of the pixel electrode layer to the maximum extent. Further, the second pixel electrode layer includes a pixel electrode block that is located in each sub pixel zone and has a lateral border located above a scan line and a longitudinal border located above a signal line so as to achieve self-shielding of light for the scan line and the signal line, allowing for omission of lateral and longitudinal black matrixes. Further, a dot-like black matrix is formed on a glass substrate at a location corresponding to a TFT on the array substrate to shield light for a site of a channel thereby simplifying the manufacturing process and increase the aperture ratio.
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