Abstract:
A thin film transistor array panel and a manufacturing method are disclosed herein. The thin film transistor array panel includes a data line, a first block of a source electrode, a third block of a drain electrode, and an electrode layer which are formed by a first metal layer disposed on a baseplate; a second block of the source electrode, a fourth block of the drain electrode are formed by a second metal layer which is disposed on the first metal layer. The first block and the second block overlap to combine integrally. The third block and the fourth block overlap to combine integrally. The present invention can decrease the electrical resistance of each of the source electrode and the drain electrode.
Abstract:
The present invention discloses an organic thin film transistor array substrate and a fabrication method thereof. The fabrication method is that a metal layer is first deposited successively on a substrate and followed by depositing a layer of Indium Tin Oxide (ITO), and then a photoresist layer is covered thereon to form a data line, a source electrode, a drain electrode and a pixel electrode by a first mask process. Subsequently, an organic semiconductor layer, a gate electrode, a scanning line, and a passivation layer are formed successively. Finally, a region where the pixel electrode, i.e. an anode of an OLED device, is situated and covered with the passivation layer is excavated an opening and allowing the underlying pixel electrode to be exposed to the outside. Then, a layer of OLED material is deposited on the exposed ITO pixel electrode to form an OLED device.
Abstract:
The present invention provides a high quality liquid crystal display pixel circuit, and a plurality of sub pixels arranged in array, and each sub pixel is divided into a main area (Main) and a sub area (Sub), and one data signal line, a voltage dividing unit (10) and a routing are provided in accordance with sub pixels of each column; a Nth data line (D(N)) is electrically coupled to the main areas (Main) of the sub pixels of Nth column and provides a main data signal voltage to the same, and the corresponding Nth routing (L(N)) is led out from the voltage dividing unit (10), and is electrically coupled to the sub areas (Sub) of the sub pixels of the next column, N+1 column and provides a sub data signal voltage acquired by performing voltage dividing to the main data signal voltage with the voltage dividing unit (10) to the same; polarities of the main data signal voltage provided by the Nth data signal line (D(N)) and the main data signal voltage provided by the next N+1th data signal line (D(N+1)) are opposite. The pixel circuit can diminish the color shift to reduce the flicker of the liquid crystal display panel and promote the display quality.
Abstract:
Disclosed are a field effect transistor and method for manufacturing the same, and a display device. The field effect transistor includes: a source and a drain which are spaced apart from each other; a semi-conductor layer arranged between the source and the drain; a first gate layer located on a side of the semi-conductor layer; and a second gate layer located on the other side of the semi-conductor layer. The field effect transistor provided by the present disclosure is less energy-consuming; a method for manufacturing the same is low costing; and a display device using the same is also less energy-consuming.
Abstract:
The present invention discloses a GOA circuit, comprising a plurality of GOA units which are cascade coupled, and the Nth stage GOA unit is employed to control charge to the Nth level scan line G(N), and the pull-down holding circuit of the Nth stage GOA unit comprises a Nth control circuit, a Nth holding circuit and a Nth shared circuit; the pull-down holding circuit of the (N+4)th stage GOA unit comprises a (N+4)th control circuit, a (N+4)th holding circuit and a Nth shared circuit; a first control end Q(N) of the Nth control circuit and a second control end receiving the first control signal regulates and controls a voltage level of the output end P(N) thereof; a first control end Q(N+4) of the (N+4)th control circuit and a second control end receiving the low frequency control signal regulates and controls a voltage level of the output end P(N+4) thereof.
Abstract:
The present application relates to a sub-pixel structure, a liquid crystal display device and a method for reducing color shift, the sub-pixel structure comprises a main area, a sub area and a signal wire, and the sub-pixel structure further comprises a first voltage dividing unit, the signal wire is connected to the main area and is connected to the sub area via the voltage dividing unit; the signal wire respectively provides different driving voltages for the main area and the sub area for reducing color shift in a liquid crystal display device. The present application has advantages on solving the color shift in relation to viewing angle in LCDs and greatly reducing cost.
Abstract:
Disclosed is a voltage conversion circuit, display panel, and method for driving the display panel. The voltage conversion circuit comprises: a voltage-dividing unit which receives a voltage of a data signal of a main pixel region, and divides the voltage of the data signal of the main pixel region so as to output an intermediate voltage, and a reverse unit which, under control of a first clock signal and a second clock signal, inversely converts the intermediate voltage to a voltage of the data signal of a sub pixel region, rendering polarity of a pixel voltage of the sub pixel region and polarity of a pixel voltage of the main pixel region opposite to each other.
Abstract:
The present invention provides a manufacture method of a TFT array substrate and a TFT array substrate structure, and the TFT array substrate structure comprises a substrate (1), a first metal electrode (2) on the substrate (1), a gate isolation layer (3) positioned on the substrate (1) and completely covering the first metal electrode (2), an island shaped semiconductor layer (4) on the gate isolation layer (3), a second metal electrode (6) on the gate isolation layer (3) and the island shaped semiconductor layer (4), a protecting layer (8) on the second metal electrode (6), a color resist layer (7) on the protecting layer (8), a protecting layer (12) on the color resist layer (7) and a first pixel electrode layer (9) on the protecting layer (12); a via (81) is formed on the protecting layer (8), the color resist layer (7) and the protecting layer (12), and an organic material layer (10) fills the inside of the via (81).
Abstract:
A liquid crystal display panel is disclosed and has data lines, scanning lines and pixel units. Each pixel units includes a first sub-pixel unit and a second sub-pixel unit. A top electrode of a first storage capacitor of the first sub-pixel unit is connected to a common electrode; a bottom electrode plate of the first storage capacitor is connected to a pixel electrode of the corresponding pixel unit. A top electrode of a second storage capacitor of the second sub-pixel unit is connected to a pixel electrode of the corresponding pixel unit; and a bottom electrode plate of the second storage capacitor is connected to the common electrode.
Abstract:
The present disclosure relates to a pixel cell circuit of compensation feedback voltage. The pixel cell circuit is provided with the compensation capacitance (C_co), one end of the compensation capacitance (C_co) electrically connects to the compensation level wirings G(m)_co, and the other end of the compensation capacitance (C_co) electrically connects to the drain of the TFT (T1) and the pixel electrode (P). A level of the compensation signals transmitted by the compensation level wirings G(m)_co is opposite to the level of the scanning signals transmitted by the scanning lines G(m). When the pixel electrode has been fully charged, the compensation capacitance generates a pull-up feedback voltage for compensating the pull-down voltage caused by the parasitic capacitance so as to eliminate the effects toward the pixel electrodes caused by the scanning signals transmitted by the scanning lines. This configuration not only decreases the flickers, but also the image sticking. In brief, the display uniformity and the display performance are enhanced.