公开(公告)号：US20110280061A1

公开(公告)日：2011-11-17

申请号：US13094863

申请日：2011-04-27

申请人： Toshihiko SAITO ,  Takanori MATSUZAKI ,  Shuhei NAGATSUKA ,  Hiroki INOUE

发明人： Toshihiko SAITO ,  Takanori MATSUZAKI ,  Shuhei NAGATSUKA ,  Hiroki INOUE

IPC分类号： G11C11/24 ,  G11C7/00

CPC分类号： H01L29/78 ,  G11C11/403 ,  G11C11/406 ,  G11C16/0416 ,  G11C2211/4065 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225

摘要： A semiconductor device includes a plurality of memory cells including a first transistor and a second transistor, a reading circuit including an amplifier circuit and a switch element, and a refresh control circuit. A first channel formation region and a second channel formation region contain different materials as their respective main components. A first gate electrode is electrically connected to one of a second source electrode and a second drain electrode. The other of the second source electrode and the second drain electrode is electrically connected to one of input terminals of the amplifier circuit. An output terminal of the amplifier circuit is connected to the other of the second source electrode and the second drain electrode through the switch element. The refresh control circuit is configured to control whether the switch element is turned on or off.

摘要翻译： 一种半导体器件包括多个包括第一晶体管和第二晶体管的存储单元，包括放大器电路和开关元件的读取电路以及刷新控制电路。 第一通道形成区域和第二通道形成区域包含不同的材料作为它们各自的主要成分。 第一栅电极电连接到第二源电极和第二漏极之一。 第二源极和第二漏极中的另一个电连接到放大器电路的一个输入端。 放大器电路的输出端子通过开关元件连接到第二源电极和第二漏电极中的另一个。 刷新控制电路被配置为控制开关元件是打开还是关闭。

公开(公告)号：US20110249487A1

公开(公告)日：2011-10-13

申请号：US13079032

申请日：2011-04-04

申请人： Toshihiko SAITO ,  Yasuyuki TAKAHASHI

发明人： Toshihiko SAITO ,  Yasuyuki TAKAHASHI

IPC分类号： G11C11/24 ,  G11C7/12

CPC分类号： G11C7/12 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/1214

摘要： A semiconductor memory device or a semiconductor device which has high reading accuracy is provided. A bit line, a word line, a memory cell placed in an intersection portion of the bit line and the word line, and a reading circuit electrically connected to the bit line are provided. The memory cell includes a first transistor and an antifuse. The reading circuit includes a pre-charge circuit, a clocked inverter, and a switch. The pre-charge circuit includes a second transistor and a NAND circuit. The semiconductor memory device includes transistor in each of which an oxide semiconductor is used in a channel formation region, as the first transistor and the second transistor.

摘要翻译： 提供了具有高读取精度的半导体存储器件或半导体器件。 提供位线，字线，放置在位线和字线的交叉部分中的存储单元，以及电连接到位线的读取电路。 存储单元包括第一晶体管和反熔丝。 读取电路包括预充电电路，时钟反相器和开关。 预充电电路包括第二晶体管和NAND电路。 半导体存储器件包括在沟道形成区域中使用氧化物半导体作为第一晶体管和第二晶体管的晶体管。

公开(公告)号：US20110241435A1

公开(公告)日：2011-10-06

申请号：US13070517

申请日：2011-03-24

申请人： Toshihiko SAITO

发明人： Toshihiko SAITO

IPC分类号： H01F38/14

CPC分类号： H04B5/0093 ,  H01F38/14 ,  H02J5/005 ,  H02J7/025 ,  H02J50/20 ,  H02J50/23 ,  H02J50/40 ,  H04B5/0037

摘要： An object of the present invention is to provide a highly reliable power supply device which can withstand long-term use. Another object of the present invention is to provide a power supply device with reduced power consumption. The power supply device includes a cell including an antenna and a switch and performing position detection operation and power feeding operation; a high-frequency wave supply circuit; a switch control circuit; and a potential detecting circuit. One electrode of the antenna is connected to the high-frequency wave supply circuit through the switch, and the other thereof is connected to the potential detecting circuit. By the position detection operation, whether there is a power receiving device which gets close to a cell or not is detected. Only when the power receiving device is detected, power is supplied by the power feeding operation.

摘要翻译： 本发明的目的是提供一种能够经受长期使用的高度可靠的供电装置。 本发明的另一个目的是提供一种降低功耗的电源装置。 电源装置包括具有天线和开关的电池，并进行位置检测动作和供电动作; 高频波供电电路; 开关控制电路; 和电位检测电路。 天线的一个电极通过开关连接到高频波供电电路，另一个连接到电位检测电路。 通过位置检测操作，检测是否存在接近单元的电力接收装置。 只有在检测到电力接收装置的情况下，才能通过供电操作来供电。

公开(公告)号：US20090201269A1

公开(公告)日：2009-08-13

申请号：US12426976

申请日：2009-04-21

申请人： Kiyoshi KATO ,  Toshihiko SAITO

发明人： Kiyoshi KATO ,  Toshihiko SAITO

IPC分类号： G06F3/044 ,  H01G5/00

CPC分类号： G02F1/13338 ,  G02F1/13306 ,  G02F1/133305 ,  G02F1/133345 ,  G02F1/13439 ,  G02F1/13454 ,  G02F1/136213 ,  G02F1/1368 ,  G02F2201/123 ,  G06F3/0412 ,  G06F3/044 ,  G09G3/36 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288 ,  H01L27/13 ,  H01L27/3244 ,  H01L29/78621 ,  H01L29/78645

摘要： As for a “system on panel” in which a control circuit and a driver circuit as well as a display device are integrally formed over a substrate such as a glass substrate, more sophistication is expected by fabricating an input unit over the same substrate. Input of a semiconductor device is generally performed by pushing or touching a button like input unit with fingers or the like. In that case, glass is often used for a counter substrate; however, it is difficult to form a button from glass and to provide it directly on the substrate due to the nature of the material. It is an object of the present invention to provide a semiconductor device at a lower price, in which the input operation can be performed without employing an external input unit.A variable capacitor is formed from a pair of electrodes and a dielectric interposed between the electrodes over a substrate, and an external input is detected by changing capacitance of the variable capacitor by a physical or electrical force. Specifically, a variable capacitor and a sense amplifier are provided over the same substrate, and the sense amplifier reads the change of capacitance of the variable capacitor and transmits a signal in accordance with the input to a control circuit.

摘要翻译： 对于在诸如玻璃基板的基板上整体地形成控制电路和驱动电路以及显示装置的“面板上的系统”，通过在相同的基板上制造输入单元，可以期待更高的精度。 半导体器件的输入通常通过用手指等按压或触摸诸如输入单元的按钮来执行。 在这种情况下，玻璃通常用于相对基板; 然而，由于材料的性质，难以从玻璃形成按钮并且将其直接提供到基板上。 本发明的目的是提供一种价格较低的半导体器件，其中可以在不使用外部输入单元的情况下执行输入操作。 可变电容器由一对电极和位于基板之间的电极之间的电介质形成，并且通过用物理或电力改变可变电容器的电容来检测外部输入。 具体地说，在同一衬底上设置可变电容器和读出放大器，读出放大器读取可变电容器的电容变化，并根据输入将信号发送到控制电路。

公开(公告)号：US20120319075A1

公开(公告)日：2012-12-20

申请号：US13599272

申请日：2012-08-30

申请人： Hajime TOKUNAGA ,  Toshihiko SAITO

发明人： Hajime TOKUNAGA ,  Toshihiko SAITO

IPC分类号： H01L45/00

CPC分类号： H01L27/112 ,  G11C17/16 ,  H01L21/84 ,  H01L27/105 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/12

摘要： A structure of a storage device which can operate memory elements utilizing silicide reaction using the same voltage value for writing and for reading, and a method for driving the same are proposed. The present invention relates to a storage device including a memory element and a circuit which changes a polarity of applying voltage to the memory element for writing (or reading) into a different polarity of that for reading (or writing). The memory element includes at least a first conductive layer, a film including silicon formed over the first conductive layer, and a second conductive layer formed over the silicon film. The first conductive layer and the second conductive layer of the memory element are formed using different materials.

摘要翻译： 提出了可以使用相同的写入和读取电压值来操作使用硅化物反应的存储元件的存储装置的结构及其驱动方法。 本发明涉及一种包括存储元件和电路的存储装置，该电路改变向用于写入（或写入）的不同极性的写入（或读取）存储元件的电压施加电压的极性。 存储元件至少包括第一导电层，在第一导电层上形成的包括硅的膜，以及形成在硅膜上的第二导电层。 存储元件的第一导电层和第二导电层使用不同的材料形成。

公开(公告)号：US20120043388A1

公开(公告)日：2012-02-23

申请号：US13287569

申请日：2011-11-02

申请人： Toshihiko SAITO ,  Yutaka SHIONOIRI ,  Kiyoshi KATO

发明人： Toshihiko SAITO ,  Yutaka SHIONOIRI ,  Kiyoshi KATO

IPC分类号： G06K19/06

CPC分类号： H01L27/12 ,  G06K19/0701 ,  G06K19/0715 ,  G06K19/0723 ,  H01L21/84

摘要： An object of the present invention is to provide a semiconductor device which can obtain the high potential necessary for writing data to a memory, using a small circuit area. In the present invention, by using as input voltage of a booster circuit not the conventionally used output VDD of a regulator circuit 104, but rather an output VDD0 of a rectifier circuit portion 103, which is a higher potential than the VDD, the high potential necessary for writing data to a memory can be obtained with a small circuit area.

摘要翻译： 本发明的目的是提供一种使用小电路区域可以获得将数据写入存储器所需的高电位的半导体器件。 在本发明中，通过使用升压电路的输入电压而不是调节器电路104的常规使用的输出VDD，而是使用比VDD高的电压的整流电路部分103的输出VDD0， 可以以小的电路面积获得将数据写入存储器所必需的。

公开(公告)号：US20110285442A1

公开(公告)日：2011-11-24

申请号：US13107167

申请日：2011-05-13

申请人： Toshihiko SAITO

发明人： Toshihiko SAITO

IPC分类号： H03K3/017

CPC分类号： H03K5/04 ,  H01L27/092 ,  H01L27/1233 ,  H01L27/1237 ,  H01L27/1251 ,  H01L29/7869

摘要： A pulse converter circuit includes a logic circuit to which a first signal is input and from which a second signal is output. The logic circuit includes a p-channel transistor which determines whether a voltage of the second signal is set to a first voltage depending on a voltage of the gate; and an n-channel transistor which determines whether the voltage of the second signal is set to a second voltage, which is higher than the first voltage, depending on a voltage of the gate. The p-channel transistor includes a semiconductor layer containing an element of a group 14. The n-channel transistor includes an oxide semiconductor layer.

摘要翻译： 脉冲转换器电路包括输入第一信号并输出​​第二信号的逻辑电路。 逻辑电路包括一个p沟道晶体管，它确定第二个信号的电压是否根据栅极的电压被设置为第一个电压; 以及n沟道晶体管，其根据栅极的电压确定第二信号的电压是否被设定为高于第一电压的第二电压。 p沟道晶体管包括含有组14的元件的半导体层.n沟道晶体管包括氧化物半导体层。

公开(公告)号：US20100265754A1

公开(公告)日：2010-10-21

申请号：US12759725

申请日：2010-04-14

申请人： Toshihiko SAITO

发明人： Toshihiko SAITO

IPC分类号： G11C17/00 ,  G11C5/14

CPC分类号： G11C5/145 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

摘要： When writing into an antifuse memory element finishes, a value of resistance of the memory element rapidly decreases; accordingly, an output voltage of a boosting circuit which produces a writing voltage rapidly decreases. By detecting a change in the output voltage of the boosting circuit to control a writing command, the writing operation can be stopped immediately after the memory element is shorted. Thus, unnecessary current consumption caused by continuing a writing operation on the shorted memory element can be suppressed.

摘要翻译： 当写入反熔丝存储元件时，存储元件的电阻值迅速降低; 因此，产生写入电压的升压电路的输出电压急剧下降。 通过检测升压电路的输出电压的变化来控制写入命令，可以在存储元件短路之后立即停止写入操作。 因此，可以抑制对短路存储元件继续写入操作引起的不必要的电流消耗。

公开(公告)号：US20110249502A1

公开(公告)日：2011-10-13

申请号：US13078019

申请日：2011-04-01

申请人： Toshihiko SAITO

发明人： Toshihiko SAITO

IPC分类号： G11C16/26 ,  G11C7/00 ,  G11C17/00

CPC分类号： G11C16/06 ,  G11C16/26

摘要： The semiconductor device includes the read circuit which reads data written to a memory cell. The read circuit includes a first transistor, a second transistor, a first switch, and a second switch. A first terminal of the first transistor is electrically connected to a gate of the first transistor, and a second terminal of the first transistor is electrically connected to an output from the read circuit via the first switch. A first terminal of the second transistor is electrically connected to a gate of the second transistor, and a second terminal of the second transistor is electrically connected to the output from the read circuit via the second switch. A channel formation region of the first transistor can be formed using an oxide semiconductor, and a channel formation region of the second transistor can be formed using silicon.

摘要翻译： 半导体器件包括读取写入存储单元的数据的读取电路。 读取电路包括第一晶体管，第二晶体管，第一开关和第二开关。 第一晶体管的第一端子电连接到第一晶体管的栅极，并且第一晶体管的第二端子经由第一开关电连接到来自读取电路的输出端。 第二晶体管的第一端子电连接到第二晶体管的栅极，并且第二晶体管的第二端子经由第二开关电连接到来自读取电路的输出端。 可以使用氧化物半导体形成第一晶体管的沟道形成区域，并且可以使用硅形成第二晶体管的沟道形成区域。

公开(公告)号：US20110080788A1

公开(公告)日：2011-04-07

申请号：US12892121

申请日：2010-09-28

申请人： Toshihiko SAITO

发明人： Toshihiko SAITO

IPC分类号： G11C16/04

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C16/34

摘要： It is an object to reduce defects caused by reading wrong data by judging whether a storage state held in a non-volatile memory element is correct or not in the case where accumulation or discharge of electrons in/from a charge accumulation layer.A semiconductor memory circuit including a memory cell region and a test region and a control circuit are included in a semiconductor device of the present invention. In the control circuit, a first operation is performed for writing data to a memory cell, and writing a first storage state to a first region or writing a second storage state to a second region. Then, a second operation is performed for reading a first storage state or a second storage state from a first region and a second region. Further, a third operation is performed for reading data from the memory cell. Whether the third operation is correctly performed or not is judged in accordance with whether the first storage state is read from the first region or not or whether the second storage state is read from the second region or not in the second operation.

摘要翻译： 本发明的目的是通过在电荷累积或电荷累积或电荷累积或放电的情况下判断在非易失性存储元件中保持的存储状态是否正确，从而减少读取错误数据所引起的缺陷。 包括存储单元区域和测试区域的半导体存储器电路和控制电路包括在本发明的半导体器件中。 在控制电路中，执行第一操作以将数据写入存储单元，并将第一存储状态写入第一区域或将第二存储状态写入第二区域。 然后，执行从第一区域和第二区域读取第一存储状态或第二存储状态的第二操作。 此外，执行用于从存储单元读取数据的第三操作。 根据从第一区域读取第一存储状态还是在第二操作中是否从第二区域读取第二存储状态来判断第三操作是否被正确执行。