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    Method of forming split gate memory cells
    12.
    发明授权
    Method of forming split gate memory cells 有权

    公开(公告)号：US11081553B2

    公开(公告)日：2021-08-03

    申请号：US16868143

    申请日：2020-05-06

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Leo Xing ,  Chunming Wang ,  Guo Yong Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

    IPC: H01L21/00 ,  H01L21/28 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/423 ,  H01L21/265 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/788

    Abstract: A method of forming a memory device includes forming a second insulation layer on a first conductive layer formed on a first insulation layer formed on semiconductor substrate. A trench is formed into the second insulation layer extending down and exposing a portion of the first conductive layer, which is etched or oxidized to have a concave upper surface. Two insulation spacers are formed along sidewalls of the trench, having inner surfaces facing each other and outer surfaces facing away from each other. A source region is formed in the substrate between the insulation spacers. The second insulation layer and portions of the first conductive layer are removed to form floating gates under the insulation spacers. A third insulation layer is formed on side surfaces of the floating gates. Two conductive spacers are formed along the outer surfaces. Drain regions are formed in the substrate adjacent the conductive spacers.

    Method Of Forming Split-Gate Flash Memory Cell With Spacer Defined Floating Gate And Discretely Formed Polysilicon Gates
    13.
    发明申请
    Method Of Forming Split-Gate Flash Memory Cell With Spacer Defined Floating Gate And Discretely Formed Polysilicon Gates 有权

    公开(公告)号：US20210005724A1

    公开(公告)日：2021-01-07

    申请号：US16796412

    申请日：2020-02-20

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chunming Wang ,  Xian Liu ,  Nhan Do ,  Leo Xing ,  Guo Yong Liu ,  Melvin Diao

    IPC: H01L21/28 ,  H01L27/11521

    Abstract: A method of forming a memory device that includes forming a first polysilicon layer using a first polysilicon deposition over a semiconductor substrate, forming an insulation spacer on the first polysilicon layer, and removing some of the first polysilicon layer to leave a first polysilicon block under the insulation spacer. A source region is formed in the substrate adjacent a first side surface of the first polysilicon block. A second polysilicon layer is formed using a second polysilicon deposition. The second polysilicon layer is partially removed to leave a second polysilicon block over the substrate and adjacent to a second side surface of the first polysilicon block. A third polysilicon layer is formed using a third polysilicon deposition. The third polysilicon layer is partially removed to leave a third polysilicon block over the source region. A drain region is formed in the substrate adjacent to the second polysilicon block.

    Method Of Making Split Gate Non-volatile Flash Memory Cell
    14.
    发明申请
    Method Of Making Split Gate Non-volatile Flash Memory Cell 审中-公开

    公开(公告)号：US20200020789A1

    公开(公告)日：2020-01-16

    申请号：US16576370

    申请日：2019-09-19

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

    IPC: H01L29/66 ,  H01L27/11521 ,  H01L21/3213

    Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

    Method Of Forming Pairs Of Three-Gate Non-volatile Flash Memory Cells Using Two Polysilicon Deposition Steps
    15.
    发明申请
    Method Of Forming Pairs Of Three-Gate Non-volatile Flash Memory Cells Using Two Polysilicon Deposition Steps 审中-公开

    公开(公告)号：US20190148529A1

    公开(公告)日：2019-05-16

    申请号：US16245069

    申请日：2019-01-10

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Feng Zhou ,  Xian Liu ,  Chieng-Sheng Su ,  Nhan Do ,  Chunming Wang

    IPC: H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L49/02 ,  H01L27/07 ,  H01L29/08 ,  H01L29/788

    Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

    Split-gate, twin-bit non-volatile memory cell
    16.
    发明授权
    Split-gate, twin-bit non-volatile memory cell 有权

    公开(公告)号：US09972632B2

    公开(公告)日：2018-05-15

    申请号：US15476663

    申请日：2017-03-31

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chunming Wang ,  Nhan Do

    IPC: H01L27/11521 ,  H01L29/423 ,  G11C16/10 ,  G11C16/16

    CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328

    Abstract: A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region adjacent to the first region. A second floating gate is disposed over and insulated from a second portion of the channel region adjacent to the second region. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. A first erase gate disposed over and insulated from the first region. A second erase gate disposed is over and insulated from the second region.

    Method Of Making Split Gate Non-volatile Flash Memory Cell
    17.
    发明申请
    Method Of Making Split Gate Non-volatile Flash Memory Cell 审中-公开

    公开(公告)号：US20170338330A1

    公开(公告)日：2017-11-23

    申请号：US15494499

    申请日：2017-04-22

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

    IPC: H01L29/66 ,  H01L27/11521 ,  H01L21/3213

    CPC classification number: H01L29/66825 ,  H01L21/32133 ,  H01L27/11521 ,  H01L29/42328

    Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

    Split-Gate, Twin-Bit Non-volatile Memory Cell
    18.
    发明申请
    Split-Gate, Twin-Bit Non-volatile Memory Cell 有权

    公开(公告)号：US20170317093A1

    公开(公告)日：2017-11-02

    申请号：US15476663

    申请日：2017-03-31

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chunming Wang ,  Nhan Do

    IPC: H01L27/11521 ,  G11C16/10 ,  G11C16/16 ,  H01L29/423

    CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328

    Abstract: A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region adjacent to the first region. A second floating gate is disposed over and insulated from a second portion of the channel region adjacent to the second region. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. A first erase gate disposed over and insulated from the first region. A second erase gate disposed is over and insulated from the second region.

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