公开(公告)号：US10818680B2

公开(公告)日：2020-10-27

申请号：US16578104

申请日：2019-09-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

IPC: H01L27/11531 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L27/11521 ,  H01L29/78 ,  H01L29/788

Abstract: A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.

公开(公告)号：US20200176578A1

公开(公告)日：2020-06-04

申请号：US16208288

申请日：2018-12-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L27/11521 ,  H01L29/66 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L29/788

Abstract: A memory cell is formed on a semiconductor substrate having an upper surface with a plurality of upwardly extending fins. First and second fins extend in one direction, and a third fin extends in an orthogonal direction. Spaced apart source and drain regions are formed in each of the first and second fins, defining a channel region extending there between in each of the first and second fins. The source regions are disposed at intersections between the third fin and the first and second fins. A floating gate is disposed laterally between the first and second fins, and laterally adjacent to the third fin, and extends along first portions of the channel regions. A word line gate extends along second portions of the channel regions. A control gate is disposed over the floating gate. An erase gate is disposed over the source regions and the floating gate.

公开(公告)号：US20160254269A1

公开(公告)日：2016-09-01

申请号：US14639063

申请日：2015-03-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Vipin Tiwari ,  Nhan Do ,  Xian Liu ,  Xiaozhou Qian ,  Ning Bai ,  Kai Man Yue

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/423

CPC classification number: H01L27/11524 ,  H01L23/57 ,  H01L27/11226 ,  H01L27/11233 ,  H01L27/11253 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

Abstract translation: 一种存储器件，其包括多个ROM单元，每个ROM单元具有形成在衬底中的间隔开的源极和漏极区域，其间具有沟道区域，设置在沟道区域的第一部分上方并与沟道区域的第一部分绝缘的第一栅极， 与沟道区的第二部分绝缘，以及在多个ROM单元上延伸的导电线。 导电线电耦合到ROM单元的第一子组的漏极区域，并且不电耦合到ROM单元的第二子组的漏极区域。 或者，ROM单元的第一子组各自包括沟道区域中的较高电压阈值注入区域，而ROM单元的第二子组每个在沟道区域中都缺少任何较高电压阈值注入区域。

公开(公告)号：US09293204B2

公开(公告)日：2016-03-22

申请号：US14252929

申请日：2014-04-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Jinho Kim ,  Xian Liu

IPC: H01L29/788 ,  H01L27/115 ,  G11C16/04 ,  G11C16/14 ,  H01L29/66 ,  H01L29/423

CPC classification number: G11C16/14 ,  G11C16/0416 ,  H01L27/11521 ,  H01L27/11553 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7889

Abstract: A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. A control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. An erase gate is disposed at least partially over and insulated from the floating gate. An electrically conductive coupling gate is disposed in the trench, adjacent to and insulated from the floating gate, and over and insulated from the source region.

Abstract translation: 存储器件及其制造方法，其中将沟槽形成为半导体材料的衬底。 源极区形成在沟槽下方，并且源极和漏极区域之间的沟道区域包括基本上沿着沟槽的侧壁延伸的第一部分和基本上沿着衬底的表面延伸的第二部分。 浮栅设置在沟槽中，与沟道区第一部分绝缘，用于控制其导电性。 控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘，以控制其导电性。 擦除栅极至少部分地布置在浮栅上并与浮栅绝缘。 导电耦合栅极设置在沟槽中，与浮动栅极相邻并与其隔离，并且与源极区域隔离并且绝缘。

公开(公告)号：US20160027517A1

公开(公告)日：2016-01-28

申请号：US14486687

申请日：2014-09-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Nhan Do ,  Yuri Tkachev ,  Kai Man Yue ,  Xiaozhou Qian ,  Ning Bai

IPC: G11C16/14

CPC classification number: G11C16/14 ,  G11C16/0425 ,  G11C16/12 ,  G11C16/16 ,  G11C29/021 ,  G11C29/028

Abstract: A system and method to inhibit the erasing of a portion of a sector of split gate flash memory cells while allowing the remainder of the sector to be erased is disclosed. The inhibiting is controlled by control logic that applies one or more bias voltages to the portion of the sector whose erasure is to be inhibited.

Abstract translation: 公开了一种抑制扇区的分割门闪存单元的一部分擦除同时允许扇区的其余部分被擦除的系统和方法。 禁止由控制逻辑控制，该控制逻辑将一个或多个偏置电压施加到要擦除擦除的扇区的该部分。

公开(公告)号：US20240257880A1

公开(公告)日：2024-08-01

申请号：US18104228

申请日：2023-01-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Louisa Schneider ,  Xian Liu ,  Steven Lemke ,  Parviz Ghazavi ,  Jinho Kim ,  Henry A. Om'Mani ,  Hieu Van Tran ,  Nhan Do

IPC: G11C16/16 ,  H01L23/48 ,  H01L29/423 ,  H10B41/10 ,  H10B41/27

CPC classification number: G11C16/16 ,  H01L23/481 ,  H01L29/42328 ,  H10B41/10 ,  H10B41/27

Abstract: A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region. A strap region is disposed between first and second pluralities of the columns. For one memory cell row, a dummy floating gate is disposed in the strap region, an erase gate line electrically connects together the erase gates of the memory cells in the one row and in the first plurality of columns, wherein the erase gate line is aligned with the dummy floating gate with a row direction gap between the erase gate line and the dummy floating gate.

公开(公告)号：US12020762B2

公开(公告)日：2024-06-25

申请号：US17576754

申请日：2022-01-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Yuri Tkachev ,  Jinho Kim ,  Cynthia Fung ,  Gilles Festes ,  Bernard Bertello ,  Parviz Ghazavi ,  Bruno Villard ,  Jean Francois Thiery ,  Catherine Decobert ,  Serguei Jourba ,  Fan Luo ,  Latt Tee ,  Nhan Do

IPC: G11C29/50

CPC classification number: G11C29/50004 ,  G11C2029/5006

Abstract: A method of testing non-volatile memory cells formed on a die includes erasing the memory cells and performing a first read operation to determine a lowest read current RC1 for the memory cells and a first number N1 of the memory cells having the lowest read current RC1. A second read operation is performed to determine a second number N2 of the memory cells having a read current not exceeding a target read current RC2. The target read current RC2 is equal to the lowest read current RC1 plus a predetermined current value. The die is determined to be acceptable if the second number N2 is determined to exceed the first number N1 plus a predetermined number. The die is determined to be defective if the second number N2 is determined not to exceed the first number N1 plus the predetermined number.

公开(公告)号：US11594453B2

公开(公告)日：2023-02-28

申请号：US17716950

申请日：2022-04-08

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L21/77 ,  H01L27/11517 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

Abstract: A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.

公开(公告)号：US20200013789A1

公开(公告)日：2020-01-09

申请号：US16578104

申请日：2019-09-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

IPC: H01L27/11531 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L27/11521 ,  H01L29/78 ,  H01L29/788

Abstract: A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.

公开(公告)号：US20190326305A1

公开(公告)日：2019-10-24

申请号：US15957615

申请日：2018-04-19

Applicant: Silicon Storage Technology, Inc.

Inventor： FENG ZHOU ,  Jinho Kim ,  Xian Liu ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L29/66

Abstract: A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.