公开(公告)号：US20220231037A1

公开(公告)日：2022-07-21

申请号：US17716950

申请日：2022-04-08

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  CATHERINE DECOBERT ,  FENG ZHOU ,  JINHO KIM ,  XIAN LIU ,  NHAN DO

IPC: H01L27/11517 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

Abstract: A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.

公开(公告)号：US20200176459A1

公开(公告)日：2020-06-04

申请号：US16208150

申请日：2018-12-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  JINHO KIM ,  XIAN LIU ,  SERGUEI JOURBA ,  CATHERINE DECOBERT ,  NHAN DO

IPC: H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

Abstract: A memory device having plurality of upwardly extending semiconductor substrate fins, a memory cell formed on a first fin and a logic device formed on a second fin. The memory cell includes source and drain regions in the first fin with a channel region therebetween, a polysilicon floating gate extending along a first portion of the channel region including the side and top surfaces of the first fin, a metal select gate extending along a second portion of the channel region including the side and top surfaces of the first fin, a polysilicon control gate extending along the floating gate, and a polysilicon erase gate extending along the source region. The logic device includes source and drain regions in the second fin with a second channel region therebetween, and a metal logic gate extending along the second channel region including the side and top surfaces of the second fin.

公开(公告)号：US20190172529A1

公开(公告)日：2019-06-06

申请号：US16273337

申请日：2019-02-12

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  XIAN LIU ,  VIPIN TIWARI ,  HIEU VAN TRAN

IPC: G11C11/419 ,  H01L29/788 ,  H01L29/66 ,  G11C16/14 ,  G11C16/04 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11521

Abstract: A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.

公开(公告)号：US20170103991A1

公开(公告)日：2017-04-13

申请号：US15264457

申请日：2016-09-13

Applicant: Silicon Storage Technology, Inc.

Inventor： JINHO KIM ,  CHIEN-SHENG SU ,  FENG ZHOU ,  XIAN LIU ,  NHAN DO ,  PRATEEP TUNTASOOD ,  PARVIZ GHAZAVI

IPC: H01L27/115

CPC classification number: H01L27/11531 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543

Abstract: A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas.