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    SUBSTRATE STRUCTURE, FABRICATION METHOD THEREOF AND CONDUCTIVE STRUCTURE
    11.
    发明申请
    SUBSTRATE STRUCTURE, FABRICATION METHOD THEREOF AND CONDUCTIVE STRUCTURE 有权
    基板结构，其制造方法及导电结构

    公开(公告)号：US20160358873A1

    公开(公告)日：2016-12-08

    申请号：US14981549

    申请日：2015-12-28

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Hsin-Ta Lin ,  Ching-Wen Chiang

    IPC: H01L23/00 ,  H01L21/768

    CPC classification number: H01L24/13 ,  H01L21/4846 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/11 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13016 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/2064

    Abstract: A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and exposing the conductive pads; a plurality of conductive vias formed in the insulating layer and electrically connected to the conductive pads; a plurality of circuits formed on the conductive vias and in the insulating layer, wherein the circuits are greater in width than the conductive vias; and a plurality of conductive posts formed on the circuits and the insulating layer, wherein each of the conductive posts has a width greater than or equal to that of each of the circuits. The conductive vias, the circuits and the conductive posts are integrally formed. As such, micro-chips or fine-pitch conductive pads can be electrically connected to the substrate structure in a flip-chip manner.

    Abstract translation: 提供了一种衬底结构，其包括：具有多个导电焊盘的衬底本体; 绝缘层，形成在所述基板主体上并暴露所述导电焊盘; 形成在所述绝缘层中并电连接到所述导电焊盘的多个导电通孔; 形成在导电通孔和绝缘层中的多个电路，其中电路的宽度大于导电通孔的宽度; 以及形成在电路和绝缘层上的多个导电柱，其中每个导电柱具有大于或等于每个电路的宽度的宽度。 导电通孔，电路和导电柱一体形成。 因此，微芯片或细间距导电焊盘可以倒装芯片方式电连接到衬底结构。

    Electronic package and fabrication method thereof and substrate structure
    12.
    发明授权
    Electronic package and fabrication method thereof and substrate structure 有权

    公开(公告)号：US10049973B2

    公开(公告)日：2018-08-14

    申请号：US14984256

    申请日：2015-12-30

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

    IPC: H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L21/683 ,  H01L21/56 ,  H01L23/31

    Abstract: A substrate structure is provided, which includes: a substrate body having opposite first and second surfaces; a plurality of conductive posts formed on the first surface of the substrate body and electrically connected to the substrate body; and a dielectric layer formed on the first surface of the substrate body for encapsulating the conductive posts, wherein one end surfaces of the conductive posts are exposed from the dielectric layer. Therefore, the present invention replaces the conventional silicon substrate with the dielectric layer so as to eliminate the need to fabricate the conventional TSVs (Through Silicon Vias) and thereby greatly reduce the fabrication cost. The present invention further provides an electronic package having the substrate structure and a fabrication method thereof.

    ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF AND SUBSTRATE STRUCTURE
    14.
    发明申请
    ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF AND SUBSTRATE STRUCTURE 审中-公开
    电子封装及其制造方法及基板结构

    公开(公告)号：US20160276256A1

    公开(公告)日：2016-09-22

    申请号：US14984256

    申请日：2015-12-30

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

    IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

    CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5384 ,  H01L23/5389 ,  H01L2221/68331 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/81005 ,  H01L2924/15311

    Abstract: A substrate structure is provided, which includes: a substrate body having opposite first and second surfaces; a plurality of conductive posts formed on the first surface of the substrate body and electrically connected to the substrate body; and a dielectric layer formed on the first surface of the substrate body for encapsulating the conductive posts, wherein one end surfaces of the conductive posts are exposed from the dielectric layer. Therefore, the present invention replaces the conventional silicon substrate with the dielectric layer so as to eliminate the need to fabricate the conventional TSVs (Through Silicon Vias) and thereby greatly reduce the fabrication cost. The present invention further provides an electronic package having the substrate structure and a fabrication method thereof.

    Abstract translation: 提供了一种基板结构，其包括：具有相对的第一和第二表面的基板主体; 形成在所述基板主体的所述第一表面上并电连接到所述基板主体的多个导电柱; 以及形成在所述基板主体的第一表面上用于封装所述导电柱的电介质层，其中所述导电柱的一个端面从所述电介质层露出。 因此，本发明用传统的硅衬底替代传统的硅衬底，以消除制造常规TSV（通硅通孔）的需要，从而大大降低制造成本。 本发明还提供一种具有基板结构的电子封装及其制造方法。

    Interposer and method of manufacturing the same
    16.
    发明授权
    Interposer and method of manufacturing the same 有权
    插件及其制造方法

    公开(公告)号：US09196596B2

    公开(公告)日：2015-11-24

    申请号：US14013469

    申请日：2013-08-29

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Wei-Jen Chang ,  Hsien-Wen Chen

    IPC: H01L23/00

    CPC classification number: H01L24/14 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/64 ,  H01L24/67 ,  H01L2924/15788 ,  H01L2924/00

    Abstract: A method of manufacturing an interposer is provided, including forming a plurality of first openings on one surface side of a substrate, forming a first metal layer in the first openings, forming on the other surface side of the substrate a plurality of second openings that are in communication with the first openings, forming a second metal layer in the second openings, and electrically connecting the first metal layer to the second metal layer, so as to form conductive through holes. The conductive through holes are formed stage by stage, such that the fabrication time in forming the metal layers is reduced, and a metal material will not be accumulated too thick on a surface of the substrate. Therefore, the metal material has a smoother surface, and no overburden will be formed around end surfaces of the through holes. An interposer is also provided.

    Abstract translation: 提供一种制造插入件的方法，包括在基板的一个表面侧上形成多个第一开口，在第一开口中形成第一金属层，在基板的另一表面侧上形成多个第二开口， 与所述第一开口连通，在所述第二开口中形成第二金属层，并且将所述第一金属层电连接到所述第二金属层，以形成导电通孔。 导电通孔逐级形成，使得形成金属层的制造时间减少，并且金属材料在基板的表面上不会太累积。 因此，金属材料具有更平滑的表面，并且在通孔的端面周围不会形成覆盖层。 还提供了插入器。

    Package structure and fabrication method thereof
    17.
    发明授权
    Package structure and fabrication method thereof 有权

    公开(公告)号：US10249562B2

    公开(公告)日：2019-04-02

    申请号：US14610910

    申请日：2015-01-30

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

    IPC: H05K1/18 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538

    Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a recess; disposing an electronic element in the recess of the carrier; forming an insulating layer in the recess to encapsulate the electronic element; forming a circuit structure on the carrier, wherein the circuit structure is electrically connected to the electronic element; forming a plurality of through holes penetrating the carrier; and forming a conductive material in the through holes to form a plurality of conductors, wherein the conductors are electrically connected to the circuit structure. By using the carrier as a substrate body, the present invention avoids warping of the package structure.

    Method of fabricating substrate structure
    18.
    发明授权
    Method of fabricating substrate structure 有权

    公开(公告)号：US10199345B2

    公开(公告)日：2019-02-05

    申请号：US15867008

    申请日：2018-01-10

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Hsin-Ta Lin ,  Ching-Wen Chiang

    IPC: H01L21/4763 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31

    Abstract: A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and exposing the conductive pads; a plurality of conductive vias formed in the insulating layer and electrically connected to the conductive pads; a plurality of circuits formed on the conductive vias and in the insulating layer, wherein the circuits are greater in width than the conductive vias; and a plurality of conductive posts formed on the circuits and the insulating layer, wherein each of the conductive posts has a width greater than or equal to that of each of the circuits. The conductive vias, the circuits and the conductive posts are integrally formed. As such, micro-chips or fine-pitch conductive pads can be electrically connected to the substrate structure in a flip-chip manner.

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