公开(公告)号：US5515517A

公开(公告)日：1996-05-07

申请号：US357052

申请日：1994-12-14

申请人： Yasuyuki Nozuyama ,  Kazuhiko Ohashi

发明人： Yasuyuki Nozuyama ,  Kazuhiko Ohashi

IPC分类号： G06F11/22 ,  G01R31/3185 ,  G06F11/26

CPC分类号： G01R31/318541 ,  G01R31/318536

摘要： A data processing device with a test circuit has a plurality of macro blocks, a common bus for transferring the output of one of the macro blocks to the other macro blocks, and a tri-state buffer incorporated into each macro block. A bus control circuit selects the tri-state buffer in a normal operation mode in which the device performs its normal functions, in order to transfer the information stored in the macro block corresponding to the tri-state buffer selected by the bus control circuit to the common bus. A selecting control circuit, which includes a selector, an AND gate, and a flip-flop (F/F), is used for selecting the tri-state buffer in a test operation mode which the device has entered, then for transferring the information stored in the macro block corresponding to the tri-state buffer selected by the selecting control circuit to the common bus. A F/F is provided for setting the device in either the normal operation mode or the test operation mode. In the data processing device according to the present invention, in addition to the bus control circuit, which is used in the normal operation mode, the selecting control circuit, which is used in the test operation mode, is provided, so that the efficiency of the test vector generation is greatly improved.

摘要翻译： 具有测试电路的数据处理装置具有多个宏块，用于将宏块中的一个的输出传送到其他宏块的公共总线，以及并入每个宏块中的三态缓冲器。 总线控制电路在设备执行其正常功能的正常操作模式中选择三态缓冲器，以将存储在与由总线控制电路选择的三态缓冲器相对应的宏块中的信息传送到 公车 包括选择器，与门和触发器（F / F）的选择控制电路用于在设备输入的测试操作模式中选择三态缓冲器，然后用于传送信息 存储在与由选择控制电路选择的三态缓冲器对应的宏块中的公共总线。 提供F / F用于在正常操作模式或测试操作模式下设置设备。 在根据本发明的数据处理装置中，除了在正常操作模式下使用的总线控制电路之外，还提供了在测试操作模式中使用的选择控制电路， 测试向量生成得到很大的改善。

公开(公告)号：US07679438B2

公开(公告)日：2010-03-16

申请号：US12118803

申请日：2008-05-12

申请人： Kazuki Tateoka ,  Masahiko Inamori ,  Shingo Matsuda ,  Kazuhiko Ohashi ,  Haruhiko Koizumi

发明人： Kazuki Tateoka ,  Masahiko Inamori ,  Shingo Matsuda ,  Kazuhiko Ohashi ,  Haruhiko Koizumi

IPC分类号： H03F3/68

CPC分类号： H03F3/189 ,  H03F1/56 ,  H03F2200/222 ,  H03F2200/255 ,  H03F2200/387 ,  H03F2200/423 ,  H03F2203/7233

摘要： A small, high performance, multifunctional high frequency circuit that is multiband and multimode compatible reduces loss from a switch formed on the output side of a final stage amplification unit. The final stage amplification unit power amplifies an input signal and outputs an amplified signal. A first matching circuit impedance converts the amplified signal input thereto at a first input impedance, and outputs a first impedance-converted signal at a first output impedance. A control unit that generates a control signal denoting signal path selection information. A switch unit selects one of at least two signal paths based on the control signal, passes the first impedance-converted signal at an on impedance through the selected path, and outputs the pass signal. A second matching circuit impedance converts a pass signal input thereto at a second input impedance, and outputs a second impedance-converted signal at a second output.

摘要翻译： 多频和多模兼容的小型，高性能，多功能高频电路可以减少在最终级放大单元输出侧形成的开关损耗。 最终级放大单元功率放大输入信号并输出​​放大信号。 第一匹配电路阻抗以第一输入阻抗转换输入到其的放大信号，并输出第一输出阻抗的第一阻抗转换信号。 控制单元，其生成表示信号路径选择信息的控制信号。 开关单元基于控制信号选择至少两个信号路径中的一个，将通过所选路径的导通阻抗的第一阻抗转换信号传递，并输出通过信号。 第二匹配电路阻抗以第二输入阻抗转换输入到其的通过信号，并在第二输出端输出第二阻抗转换信号。

公开(公告)号：US07190982B2

公开(公告)日：2007-03-13

申请号：US10764537

申请日：2004-01-27

申请人： Kouki Yamamoto ,  Noriyuki Yoshikawa ,  Kazuhiko Ohashi

发明人： Kouki Yamamoto ,  Noriyuki Yoshikawa ,  Kazuhiko Ohashi

IPC分类号： H04M1/00

CPC分类号： H05K5/0091 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K3/3405 ,  H05K9/0039 ,  H01L2924/00014

摘要： In the present radio frequency device, a radio frequency circuit part and a transmission line are disposed on the top surface of a circuit board on the surface of which a ground pattern is provided, and a metal shielding cap is fixed to the circuit board so as to cover the radio frequency circuit part and the transmission path. The metal shielding cap includes: a top plate disposed above the radio frequency circuit part and substantially parallel to the circuit board; a grounded side wall being provided so as to hang down from a part of an edge of the top plate, having a spring property and being joined to the ground pattern of the circuit board, and a side wall is open except for the grounded side wall.

摘要翻译： 在本射频装置中，射频电路部分和传输线设置在电路板的设置有接地图案的表面的顶表面上，金属屏蔽帽固定到电路板上，以便 以覆盖射频电路部分和传输路径。 金属屏蔽盖包括：顶板，设置在射频电路部分上方并且基本上平行于电路板; 接地侧壁设置成从顶板的边缘的一部分悬挂起来，具有弹簧特性并且接合到电路板的接地图案，并且侧壁是开放的，除了接地的侧壁 。

公开(公告)号：US06849934B2

公开(公告)日：2005-02-01

申请号：US10382356

申请日：2003-03-05

申请人： Makoto Ogawa ,  Akira Urakami ,  Kazuhiko Ohashi

发明人： Makoto Ogawa ,  Akira Urakami ,  Kazuhiko Ohashi

IPC分类号： C09J7/02 ,  C09J7/04 ,  H01L23/12 ,  H01L23/14 ,  H01L23/498 ,  H05K1/03 ,  H05K3/46 ,  H01L23/02

CPC分类号： H05K3/4688 ,  C09J7/21 ,  C09J7/22 ,  C09J7/35 ,  C09J2400/263 ,  C09J2427/006 ,  H01L23/49894 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/034 ,  H05K3/4605 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2203/1147 ,  Y10T428/24917 ,  Y10T428/249958

摘要： A dielectric film for a printed wiring board that has excellent heat resistance, moisture resistance, insulation properties, adhesiveness, ease of handling, ease of processing, and the like, and possesses low elasticity and high elongation as stress relief functions. The dielectric film has drawn porous polytetrafluoroethylene used as the base material; this is impregnated with an adhesive or fusible resin; the post-solidification tensile modulus of elasticity is 0.1 to 1.8 GPa; and the tensile elongation at break (at 25° C.) is at least 4.0%. A semiconductor device, comprising a multilayer printed board having a plurality of circuit layers, and a semiconductor element mounted on the multilayer printed board, this semiconductor device having an insulating/adhesive layer with a stress relief function between the outermost circuit layer of the multilayer board on the side of the semiconductor element, and the circuit layer adjacent thereto; and the insulating/adhesive layer is formed from the dielectric film. Also, a printed wiring board therefor.

摘要翻译： 用于印刷电路板的电介质膜具有优异的耐热性，耐湿性，绝缘性，粘合性，易于操作，易于加工等优点，并且具有低弹性和高伸长率作为应力消除功能。 电介质膜采用多孔聚四氟乙烯作为基材; 这是用粘合剂或可熔树脂浸渍的; 后凝固拉伸弹性模量为0.1〜1.8GPa; 拉伸断裂伸长率（25℃）至少为4.0％。 一种半导体器件，包括具有多个电路层的多层印刷电路板和安装在多层印刷电路板上的半导体元件，该半导体器件具有在多层板的最外层电路层之间具有应力消除功能的绝缘/粘合层 在半导体元件的一侧和与其相邻的电路层; 并且绝缘/粘合剂层由电介质膜形成。 另外，也是印刷电路板。

公开(公告)号：US5693530A

公开(公告)日：1997-12-02

申请号：US480910

申请日：1995-06-07

申请人： Karel A. Schat ,  Kazuhiko Ohashi ,  Priscilla H. O'Connell

发明人： Karel A. Schat ,  Kazuhiko Ohashi ,  Priscilla H. O'Connell

IPC分类号： C12N15/09 ,  A61K31/70 ,  A61K35/76 ,  A61K38/00 ,  A61K39/00 ,  A61K39/255 ,  A61K48/00 ,  A61P31/12 ,  C07H21/02 ,  C07H21/04 ,  C07K14/055 ,  C12N15/00 ,  C12N15/38 ,  C12R1/92 ,  C12N15/86 ,  A61K39/295

CPC分类号： C07K14/005 ,  A61K38/00 ,  A61K39/00 ,  C12N2710/16322 ,  Y10S424/816 ,  Y10S930/224

摘要： A novel nucleotide sequence in the genome of Marek's disease virus (MDV) containing an open reading frame, whose expression is associated with lytic infection and tumor cell development in MDV-infected cells, is described. Also described is the use of this novel sequence for molecular diagnostics of serotype 1 MDV; and to generate a recombinant MDV by inserting one or more endogenous or exogenous genes, operably linked to a control element for expression, into a region of the MDV genome comprising the novel nucleotide sequence, wherein the insertion interrupts expression of the open reading frame.

摘要翻译： 描述了马立克氏病病毒（MDV）基因组中含有开放读框的新型核苷酸序列，其表达与MDV感染细胞中的溶解感染和肿瘤细胞发育相关。 还描述了该新型序列用于血清型1 MDV的分子诊断; 并通过将可操作地连接到用于表达的对照元件的一个或多个内源或外源基因插入到包含新核苷酸序列的MDV基因组的区域中以产生重组MDV，其中插入中断了开放阅读框的表达。

公开(公告)号：US5412258A

公开(公告)日：1995-05-02

申请号：US796585

申请日：1991-11-22

申请人： Yoshikazu Ogawa ,  Kazuhiko Ohashi

发明人： Yoshikazu Ogawa ,  Kazuhiko Ohashi

IPC分类号： G01R31/28 ,  G01R31/319 ,  H03K5/01 ,  H03K3/01 ,  H03K5/13 ,  H03L5/00

CPC分类号： H03K5/01 ,  G01R31/31924 ,  G01R31/31922

摘要： An integrated circuit testing device, including a small test signal generator for generating a small test signal having a small amplitude corresponding to a test signal supplied to an input terminal of a target integrated circuit to be tested; a test signal supply circuit for amplifying the small test signal generated from the small test signal generator to obtain the test signal having a predetermined power and timing, and for supplying the test signal to the input terminal of the target integrated circuit to be tested; and a controller for setting a rise time of the test signal and a fall time of the test signal at a predetermined time by adjusting the amount of power of the test signal supplied from the test signal supply circuit.

摘要翻译： 一种集成电路测试装置，包括：小型测试信号发生器，用于产生具有对应于被提供给待测试的目标集成电路的输入端的测试信号的小振幅的小测试信号; 测试信号供给电路，用于放大从小型测试信号发生器产生的小测试信号，以获得具有预定功率和定时的测试信号，并将测试信号提供给待测试的目标集成电路的输入端; 以及控制器，用于通过调整从测试信号提供电路提供的测试信号的功率量，在预定时间设置测试信号的上升时间和测试信号的下降时间。