公开(公告)号：US20190067290A1

公开(公告)日：2019-02-28

申请号：US15691974

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Shih-Ming Chang ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Yu-Jung Chang ,  Guo-Huei Wu

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/10823 ,  H01L21/76897 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10829

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

公开(公告)号：US12164853B2

公开(公告)日：2024-12-10

申请号：US17574048

申请日：2022-01-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Anurag Verma ,  Chi-Chun Liang ,  Meng-Kai Hsu ,  Cheng-Yu Lin ,  Pochun Wang ,  Hui-Zhong Zhuang

IPC: G06F30/392 ,  G06F30/394 ,  G06F119/18

Abstract: The present disclosure provides a method and an apparatus for generating a layout of a semiconductor device. The method includes placing a first cell and a second cell adjacent to the first cell, placing a first conductive pattern in a first track of the first cell extending in a first direction, wherein the first conductive pattern is configured as an input terminal or an output terminal of the first cell, placing a second conductive pattern in a first track of the second cell extending in the first direction, wherein the second conductive pattern is configured as an input terminal or an output terminal of the second cell, and aligning the first conductive pattern with the second conductive pattern.

公开(公告)号：US12080647B2

公开(公告)日：2024-09-03

申请号：US18065963

申请日：2022-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Guo-Huei Wu ,  Pochun Wang ,  Wei-Hsin Tsai ,  Chih-Liang Chen ,  Li-Chun Tien

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L27/092

CPC classification number: H01L23/5286 ,  H01L21/768 ,  H01L23/5226 ,  H01L27/092

Abstract: An integrated circuit includes a first power rail, a conductive structure, a first active region of a first set of transistors and a second active region of a second set of transistors. The first power rail is on a back-side of a substrate, extends in a first direction, and is configured to supply a first supply voltage. The first active region extends in the first direction, and is on a first level of a front-side of the substrate opposite from the back-side. The second active region extends in the first direction, is on the first level of the front-side of the substrate, and is separated from the first active region in a second direction different from the first direction. The conductive structure is on the back-side of the substrate, extends in the first direction, and is electrically coupled to the first active region and the second active region.

公开(公告)号：US12039242B2

公开(公告)日：2024-07-16

申请号：US17008067

申请日：2020-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pochun Wang ,  Jerry Chang Jui Kao ,  Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Tzu-Ying Lin ,  Chung-Hsing Wang

IPC: G06F30/392 ,  G06F30/3953 ,  H01L27/02 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L27/092

CPC classification number: G06F30/392 ,  G06F30/3953 ,  H01L27/0207 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/4238 ,  H01L27/092

Abstract: A layout method includes generating a design data comprising an electronic circuit, and generating a design layout by placing a first cell corresponding to the electronic circuit. The first cell includes a first source/drain region and a second source/drain region extending in a first direction in a first layer, a gate electrode extending in a second direction perpendicular to the first direction in a second layer, and a first conductive line arranged in a third layer over the second layer and electrically connected to one of the first source/drain region, the second source/drain region and the gate electrode. The first cell is defined by a left cell side and a right cell side. At least one of the left cell side, the right cell side, the gate electrode and the first conductive line extends in a third direction not parallel to the first and second directions.

公开(公告)号：US11868699B2

公开(公告)日：2024-01-09

申请号：US18065299

申请日：2022-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pochun Wang ,  Yu-Jung Chang ,  Hui-Zhong Zhuang ,  Ting-Wei Chiang

IPC: G06F30/392 ,  H01L27/092 ,  H03K19/0948 ,  H03K19/20 ,  H01L23/522 ,  H01L23/528 ,  G06F30/39

CPC classification number: G06F30/392 ,  G06F30/39 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/092 ,  H03K19/0948 ,  H03K19/20

Abstract: An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact. The first and second active regions extend in a first direction, are in a substrate, and are located on a first level. The first active region includes a first drain/source region and a second drain/source region. The second active region includes a third drain/source region. The first insulating region is over the first drain/source region. The first contact extends in a second direction, overlaps the third drain/source region, is electrically coupled to the third drain/source region and is located on a second level. The second contact extends in at least the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first drain/source region, is electrically coupled to the third drain/source region, and is located on a third level.

公开(公告)号：US20230268339A1

公开(公告)日：2023-08-24

申请号：US17744160

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pochun Wang ,  Chih-Yu LAI ,  Chi-Yu Lu ,  Shang-Hsuan CHIU ,  Hui-Zhong Zhuang ,  Chih-Liang Chen

IPC: H01L27/06 ,  H01L27/02

CPC classification number: H01L27/0617 ,  H01L27/0218

Abstract: An integrated circuit including a first cell and a second cell. The first cell includes a first plurality of active areas that extend in a first direction and a first plurality of gates that extend in a second direction that crosses the first direction, the first cell having first cell edges defined by breaks in the first plurality of gates. The second cell includes a second plurality of active areas that extend in the first direction and a second plurality of gates that extend in the second direction, the second cell having second cell edges defined by breaks in the second plurality of gates. Each of the second plurality of active areas is larger than each of the first plurality of active areas and the first cell is adjacent the second cell such that the first cell edges align with the second cell edges.

公开(公告)号：US20220310598A1

公开(公告)日：2022-09-29

申请号：US17840430

申请日：2022-06-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Guo-Huei Wu ,  Pochun Wang ,  Chih-Liang Chen ,  Li-Chun Tien

IPC: H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  G06F30/392 ,  G06F30/31 ,  H01L21/8238

Abstract: A semiconductor device includes a buried communication (com) conductor (BC) CFET including: first and second active regions arranged in a stack according to CFET-type configuration; a first layer of metallization (M_1st layer) over the stack which includes first conductors configured for data or control signals (communication (com) conductors), and power grid (PG) conductors; and a layer of metallization (M_B layer) below the stack and which includes second com conductors.

公开(公告)号：US11362110B2

公开(公告)日：2022-06-14

申请号：US16927740

申请日：2020-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pochun Wang ,  Guo-Huei Wu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Li-Chun Tien

IPC: H01L27/12 ,  H01L21/84 ,  H01L23/522 ,  H01L23/528 ,  H01L21/74 ,  H01L21/768 ,  H01L21/822 ,  H01L21/423 ,  H01L29/786 ,  H01L27/06

Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.

公开(公告)号：US11188703B2

公开(公告)日：2021-11-30

申请号：US16579138

申请日：2019-09-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Sang-Chi Huang ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Pochun Wang

IPC: G06F30/394 ,  H01L27/02 ,  G06F30/392

Abstract: A method of forming an integrated circuit includes generating a first and a second standard cell layout design, generating a first set of cut feature layout patterns extending in a first direction, and manufacturing the integrated circuit based on the first or second standard cell layout design. Generating the first standard cell layout design includes generating a first set of conductive feature layout patterns extending in the first direction, and overlapping a first set of gridlines extending in the first direction. Generating the second standard cell layout design includes generating a second set of conductive feature layout patterns extending in the first direction and overlapping a second set of gridlines extending in the first direction. A side of a first cut feature layout pattern extending in the first direction is aligned with a first gridline of the first or second set of gridlines.

公开(公告)号：US10734321B2

公开(公告)日：2020-08-04

申请号：US16135684

申请日：2018-09-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Yu-Jung Chang ,  Guo-Huei Wu ,  Shih-Ming Chang

IPC: H01L29/40 ,  H01L23/535 ,  H01L21/768 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  G06F30/39 ,  G06F30/392

Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.